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Message-ID: <94c3f7ba1caa45f7ba503cde6e0c79d2@AcuMS.aculab.com>
Date:   Fri, 31 Mar 2023 08:49:48 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Wu Zongyong' <wuzongyong@...ux.alibaba.com>,
        "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>
CC:     "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "thomas.lendacky@....com" <thomas.lendacky@....com>,
        "tony.luck@...el.com" <tony.luck@...el.com>,
        "wutu.xq2@...ux.alibaba.com" <wutu.xq2@...ux.alibaba.com>
Subject: RE: [RFC PATCH] x86/insn: support decode MOVSXD instruction for MMIO

From: Wu Zongyong
> Sent: 31 March 2023 03:24
> 
> On Thu, Mar 30, 2023 at 03:39:51PM +0300, kirill.shutemov@...ux.intel.com wrote:
> > On Wed, Mar 29, 2023 at 10:59:37AM +0800, Wu Zongyong wrote:
> > > It seems MOVSXD which opcode is 0x63 is not handled, support
> > > to decode it in insn_decode_mmio().
> >
> > Do you have a particular user in mind?
> To be honest, I don't find a specific user which uses the MOVSXD.
> 
> But both Intel and AMD's instructions reference contains MOVSXD and lots
> of MOVSXD instructions occur when I "objdump -S vmlinux", so I think it
> may be useful to support it in insn_decode_mmio().
> 
> Are there some special consideration about this instruction?

It is a sign-extending memory read (32bit to 64bit).
You pretty much never want to do that to a device register.
Also kernel code should be using readl() (etc) which do
unsigned reads.
So they should never happen for mmio.

Of course, if you mmap() PCIe space directly into a program's
address space anything might happen ...

	David

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