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Message-Id: <20230331-topic-konahana_speedbin-v3-5-2dede22dd7f7@linaro.org>
Date: Fri, 31 Mar 2023 03:14:53 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Sean Paul <sean@...rly.run>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@...aro.org>
Subject: [PATCH v3 5/5] arm64: dts: qcom: sm8250: Add GPU speedbin support
SM8250 has (at least) four GPU speed bins. With the support added on the
driver side, wire up bin detection in the DTS to restrict lower-quality
SKUs from running at frequencies they were not validated at.
Tested-by: Marijn Suijten <marijn.suijten@...ainline.org> # On Sony Xperia 5 II (speed bin 0x7)
Reviewed-by: Marijn Suijten <marijn.suijten@...ainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 7b78761f2041..65e6fcff2d6c 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -962,6 +962,18 @@ ipcc: mailbox@...000 {
#mbox-cells = <2>;
};
+ qfprom: efuse@...000 {
+ compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
+ reg = <0 0x00784000 0 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpu_speed_bin: gpu_speed_bin@19b {
+ reg = <0x19b 0x1>;
+ bits = <5 3>;
+ };
+ };
+
rng: rng@...000 {
compatible = "qcom,prng-ee";
reg = <0 0x00793000 0 0x1000>;
@@ -2559,49 +2571,58 @@ gpu: gpu@...0000 {
qcom,gmu = <&gmu>;
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
status = "disabled";
zap-shader {
memory-region = <&gpu_mem>;
};
- /* note: downstream checks gpu binning for 670 Mhz */
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-670000000 {
opp-hz = /bits/ 64 <670000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-supported-hw = <0xa>;
};
opp-587000000 {
opp-hz = /bits/ 64 <587000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-supported-hw = <0xb>;
};
opp-525000000 {
opp-hz = /bits/ 64 <525000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-supported-hw = <0xf>;
};
opp-490000000 {
opp-hz = /bits/ 64 <490000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-supported-hw = <0xf>;
};
opp-441600000 {
opp-hz = /bits/ 64 <441600000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ opp-supported-hw = <0xf>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-supported-hw = <0xf>;
};
opp-305000000 {
opp-hz = /bits/ 64 <305000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-supported-hw = <0xf>;
};
};
};
--
2.40.0
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