linux-kernel - [PATCH v7 22/22] riscv: dts: starfive: jh7110: Correct the properties of S7 core

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Message-ID: <20230401111934.130844-23-hal.feng@starfivetech.com>
Date:   Sat, 1 Apr 2023 19:19:34 +0800
From:   Hal Feng <hal.feng@...rfivetech.com>
To:     <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-riscv@...ts.infradead.org>
CC:     Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        "Rob Herring" <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor@...nel.org>,
        "Palmer Dabbelt" <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Ben Dooks <ben.dooks@...ive.com>,
        "Daniel Lezcano" <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Emil Renner Berthing <emil.renner.berthing@...onical.com>,
        Hal Feng <hal.feng@...rfivetech.com>,
        <linux-kernel@...r.kernel.org>
Subject: [PATCH v7 22/22] riscv: dts: starfive: jh7110: Correct the properties of S7 core

The S7 core has no L1 data cache and MMU, so delete some
related properties.

Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index d484ecdf93f7..4c5fdb905da8 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -20,21 +20,12 @@ cpus {
 		S7_0: cpu@0 {
 			compatible = "sifive,s7", "riscv";
 			reg = <0>;
-			d-cache-block-size = <64>;
-			d-cache-sets = <64>;
-			d-cache-size = <8192>;
-			d-tlb-sets = <1>;
-			d-tlb-size = <40>;
 			device_type = "cpu";
 			i-cache-block-size = <64>;
 			i-cache-sets = <64>;
 			i-cache-size = <16384>;
-			i-tlb-sets = <1>;
-			i-tlb-size = <40>;
-			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imac_zba_zbb";
-			tlb-split;
 			status = "disabled";
 
 			cpu0_intc: interrupt-controller {
-- 
2.38.1