linux-kernel - Re: [PATCH v1] dt-bindings: move cache controller bindings to a cache directory

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Message-ID: <168055794093.1918674.10704326537545829066.robh@kernel.org>
Date:   Mon, 3 Apr 2023 16:40:22 -0500
From:   Rob Herring <robh@...nel.org>
To:     Conor Dooley <conor@...nel.org>
Cc:     Konrad Dybcio <konrad.dybcio@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Christophe Leroy <christophe.leroy@...roup.eu>,
        Rishabh Bhatnagar <rishabhb@...eaurora.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-arm-kernel@...ts.infradead.org,
        Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>,
        Rob Herring <robh+dt@...nel.org>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Masahiro Yamada <yamada.masahiro@...ionext.com>,
        Masami Hiramatsu <mhiramat@...nel.org>,
        linuxppc-dev@...ts.ozlabs.org,
        Serge Semin <fancer.lancer@...il.com>,
        Prakash Ranjan <saiprakash.ranjan@...eaurora.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Nicholas Piggin <npiggin@...il.com>,
        linux-kernel@...r.kernel.org,
        Bjorn Andersson <andersson@...nel.org>,
        Scott Wood <oss@...error.net>, linux-arm-msm@...r.kernel.org,
        Andy Gross <agross@...nel.org>,
        Michael Ellerman <mpe@...erman.id.au>,
        devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v1] dt-bindings: move cache controller bindings to a
 cache directory


On Thu, 30 Mar 2023 18:32:56 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> There's a bunch of bindings for (mostly l2) cache controllers
> scattered to the four winds, move them to a common directory.
> I renamed the freescale l2cache.txt file, as while that might make sense
> when the parent dir is fsl, it's confusing after the move.
> The two Marvell bindings have had a "marvell," prefix added to match
> their compatibles.
> 
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
>  .../{memory-controllers => cache}/baikal,bt1-l2-ctl.yaml        | 2 +-
>  .../{powerpc/fsl/l2cache.txt => cache/freescale-l2cache.txt}    | 0
>  Documentation/devicetree/bindings/{arm => cache}/l2c2x0.yaml    | 2 +-
>  .../{arm/mrvl/feroceon.txt => cache/marvell,feroceon-cache.txt} | 0
>  .../{arm/mrvl/tauros2.txt => cache/marvell,tauros2-cache.txt}   | 0
>  .../devicetree/bindings/{arm/msm => cache}/qcom,llcc.yaml       | 2 +-
>  .../devicetree/bindings/{riscv => cache}/sifive,ccache0.yaml    | 2 +-
>  .../socionext => cache}/socionext,uniphier-system-cache.yaml    | 2 +-
>  MAINTAINERS                                                     | 2 ++
>  9 files changed, 7 insertions(+), 5 deletions(-)
>  rename Documentation/devicetree/bindings/{memory-controllers => cache}/baikal,bt1-l2-ctl.yaml (95%)
>  rename Documentation/devicetree/bindings/{powerpc/fsl/l2cache.txt => cache/freescale-l2cache.txt} (100%)
>  rename Documentation/devicetree/bindings/{arm => cache}/l2c2x0.yaml (99%)
>  rename Documentation/devicetree/bindings/{arm/mrvl/feroceon.txt => cache/marvell,feroceon-cache.txt} (100%)
>  rename Documentation/devicetree/bindings/{arm/mrvl/tauros2.txt => cache/marvell,tauros2-cache.txt} (100%)
>  rename Documentation/devicetree/bindings/{arm/msm => cache}/qcom,llcc.yaml (96%)
>  rename Documentation/devicetree/bindings/{riscv => cache}/sifive,ccache0.yaml (98%)
>  rename Documentation/devicetree/bindings/{arm/socionext => cache}/socionext,uniphier-system-cache.yaml (96%)
> 

Applied, thanks!