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Message-ID: <2703abe4-f164-2208-99ac-0935ebd41716@suse.com>
Date: Mon, 3 Apr 2023 08:57:48 +0200
From: Juergen Gross <jgross@...e.com>
To: Borislav Petkov <bp@...en8.de>
Cc: linux-kernel@...r.kernel.org, x86@...nel.org,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
Dave Hansen <dave.hansen@...ux.intel.com>,
"H. Peter Anvin" <hpa@...or.com>
Subject: Re: [PATCH v4 09/12] x86/mtrr: construct a memory map with cache
modes
On 01.04.23 16:24, Borislav Petkov wrote:
> On Fri, Mar 31, 2023 at 03:23:13PM +0200, Juergen Gross wrote:
>> In general the critical case is add_map_entry_at() returning 2 (in the
>> case it is returning 1, the index can be set to -1, but there is always
>> the "continue" statement right after that, which would execute the "i++"
>> of the "for" statement).
>>
>> add_map_entry_at() can return 2 only, if it detects "merge_prev" and
>> "merge_next". "merge_prev" can be set only if the current index was > 0,
>> which makes it impossible to return 2 if the index was 0.
>
> Yeah, in the meantime I did add some debug printks in order to find my
> way around that code...
>
>> How should it be named? AMD TOP_MEM2 MSR?
>
> It is already called that way - see "git grep TOP_MEM2" output.
>
>> The problem isn't an added MTRR register, but a possibly replaced or removed
>> one. Handling that is much more complicated, so I've chosen to do it the simple
>> way.
>
> Pls put that blurb over the function: needs to be called when MTRRs get
> modified so that the map is kept valid, yadda yadda...
Okay.
Juergen
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