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Message-ID: <CAAhSdy1L55ZOTKhv81baAMPkEQ==Oz0KgoULkq1mFx4GWN+Sow@mail.gmail.com>
Date: Mon, 3 Apr 2023 17:35:54 +0530
From: Anup Patel <anup@...infault.org>
To: Conor Dooley <conor.dooley@...rochip.com>
Cc: Anup Patel <apatel@...tanamicro.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Atish Patra <atishp@...shpatra.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Andrew Jones <ajones@...tanamicro.com>, kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, Atish Patra <atishp@...osinc.com>
Subject: Re: [PATCH v3 2/8] RISC-V: Detect AIA CSRs from ISA string
On Mon, Apr 3, 2023 at 3:10 PM Conor Dooley <conor.dooley@...rochip.com> wrote:
>
> On Mon, Apr 03, 2023 at 03:03:04PM +0530, Anup Patel wrote:
>
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 59d58ee0f68d..1b13a5823b90 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -221,8 +221,10 @@ void __init riscv_fill_hwcap(void)
> > }
> > } else {
> > /* sorted alphabetically */
> ^^^^^^^^^^^^^^^^^^^^^
>
> > + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
> > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
> > SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
> > + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
>
> This entry has been added in an incorrect order chief :/
Okay, I will update in the next revision.
>
> > SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
> > SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
> > SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
Regards,
Anup
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