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Date:   Tue, 04 Apr 2023 12:03:09 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Devi Priya <quic_devipriy@...cinc.com>
Cc:     agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        mturquette@...libre.com, sboyd@...nel.org,
        linus.walleij@...aro.org, catalin.marinas@....com, will@...nel.org,
        p.zabel@...gutronix.de, shawnguo@...nel.org, arnd@...db.de,
        marcel.ziswiler@...adex.com, dmitry.baryshkov@...aro.org,
        geert+renesas@...der.be, rafal@...ecki.pl, nfraprado@...labora.com,
        broonie@...nel.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, quic_srichara@...cinc.com,
        quic_gokulsri@...cinc.com, quic_sjaganat@...cinc.com,
        quic_kathirav@...cinc.com, quic_arajkuma@...cinc.com,
        quic_anusha@...cinc.com, quic_poovendh@...cinc.com
Subject: Re: [PATCH V11 3/4] arm64: dts: qcom: Add support for ipq9574 SoC and
 RDP433 variant

On 2023-04-04 11:16, Devi Priya wrote:
> Add initial device tree support for Qualcomm IPQ9574 SoC and
> Reference Design Platform(RDP) 433 which is based on IPQ9574
> family of SoCs
> 
> Co-developed-by: Anusha Rao <quic_anusha@...cinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@...cinc.com>
> Co-developed-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
> ---
>  Changes in V11:
> 	- Dropped the unused backup clock source bias_pll_ubi_nc_clk
> 
>  arch/arm64/boot/dts/qcom/Makefile           |   1 +
>  arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts |  84 +++++++
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi       | 263 ++++++++++++++++++++
>  3 files changed, 348 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
> 

[...]

> +		intc: interrupt-controller@...0000 {
> +			compatible = "qcom,msm-qgic2";
> +			reg = <0x0b000000 0x1000>,  /* GICD */
> +			      <0x0b002000 0x1000>,  /* GICC */

This is definitely wrong. The GICC region cannot be less than
8kB, as the GICC_DIR register is in the second 4kB region.

I'm pretty sure the kernel shouts at you when booting at EL2.

> +			      <0x0b001000 0x1000>,  /* GICH */
> +			      <0x0b004000 0x1000>;  /* GICV */

Same thing here.

> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

Missing target CPU encoding.

         M.
-- 
Jazz is not dead. It just smells funny...

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