linux-kernel - Re: [PATCH 3/3] spi: s3c64xx: support interrupt based pio mode

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Message-ID: <61a67466-3467-4f71-bc27-d660e37c08ac@sirena.org.uk>
Date:   Tue, 4 Apr 2023 13:58:18 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Jaewon Kim <jaewon02.kim@...sung.com>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Andi Shyti <andi@...zian.org>,
        Alim Akhtar <alim.akhtar@...sung.com>,
        Rob Herring <robh+dt@...nel.org>, linux-spi@...r.kernel.org,
        linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Chanho Park <chanho61.park@...sung.com>
Subject: Re: [PATCH 3/3] spi: s3c64xx: support interrupt based pio mode

On Tue, Apr 04, 2023 at 03:00:11PM +0900, Jaewon Kim wrote:

> This patch adds IRQ based PIO mode instead of cpu polling.
> By using the FIFO trigger level, interrupts are received.
> CPU consumption is reduced in PIO mode because registers are not
> constantly checked.

Is there some lower limit where it's still worth using polling, for
example for just one or two bytes like a register address?  Taking an
interrupt isn't free...

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