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Message-Id: <20230405-wharf-rejoin-5222e5958611@spud>
Date: Wed, 5 Apr 2023 22:30:45 +0100
From: Conor Dooley <conor@...nel.org>
To: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Hal Feng <hal.feng@...rfivetech.com>
Cc: conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>,
Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Ben Dooks <ben.dooks@...ive.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v7 00/22] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
From: Conor Dooley <conor.dooley@...rochip.com>
On Sat, 01 Apr 2023 19:19:12 +0800, Hal Feng wrote:
> This patch series adds basic clock, reset & DT support for StarFive
> JH7110 SoC.
>
> @Stephen and @Conor, I have made this series start with the shared
> dt-bindings, so it will be easier to merge.
>
> @Conor, patch 1, 2, 16~21 were already in your branch. Patch 22 is the
> same with the patch [1] I submitted before, which you had accepted but
> not merge it into your branch.
>
> [...]
Applied to riscv-dt-for-next, thanks!
[01/22] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
https://git.kernel.org/conor/c/7fce1e39f019
[02/22] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
https://git.kernel.org/conor/c/3de0c9103258
These two are shared with clk.
[16/22] dt-bindings: timer: Add StarFive JH7110 clint
https://git.kernel.org/conor/c/1ff5482ab9a5
[17/22] dt-bindings: interrupt-controller: Add StarFive JH7110 plic
https://git.kernel.org/conor/c/8406d19ca049
I took these bindings too, as Palmer has done that in the past for new
SoC support.
[18/22] dt-bindings: riscv: Add SiFive S7 compatible
https://git.kernel.org/conor/c/8868caa2a073
[19/22] riscv: dts: starfive: Add initial StarFive JH7110 device tree
https://git.kernel.org/conor/c/60bf0a39842e
[20/22] riscv: dts: starfive: Add StarFive JH7110 pin function definitions
https://git.kernel.org/conor/c/e22f09e598d1
[21/22] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
https://git.kernel.org/conor/c/54baba33392d
[22/22] riscv: dts: starfive: jh7110: Correct the properties of S7 core
(squashed)
Hal, can you get your folks to resend whatever dts bits that are now
applicable? IOW, the dt-bindings for the entries are in a for-next
branch for some subsystem.
Thanks,
Conor.
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