linux-kernel - Re: [PATCH] drm/sun4i: uncouple DSI dotclock divider from TCON0_DCLK

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Message-Id: <CROTQHUM88W0.2URPO95U5ZMS5@void.crly.cz>
Date:   Wed, 05 Apr 2023 14:34:11 +0200
From:   "Roman Beranek" <romanberanek@...oud.com>
To:     "Maxime Ripard" <maxime@...no.tech>
Cc:     "Frank Oltmanns" <frank@...manns.dev>,
        "Chen-Yu Tsai" <wens@...e.org>, "David Airlie" <airlied@...il.com>,
        "Daniel Vetter" <daniel@...ll.ch>,
        "Jernej Skrabec" <jernej.skrabec@...il.com>,
        "Samuel Holland" <samuel@...lland.org>,
        <dri-devel@...ts.freedesktop.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-sunxi@...ts.linux.dev>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/sun4i: uncouple DSI dotclock divider from
 TCON0_DCLK_REG

Hello Maxime,

On Wed Mar 29, 2023 at 9:58 PM CEST, Maxime Ripard wrote:
> > In order to preserve semantic correctness however, I propose to preface
> > the change with a patch that renames sun4i_dotclock and tcon-pixel-clock
> > such that dot/pixel is replaced with d/data. What do you think?
>
> I don't think it's exposed to the userspace in any way so it makes sense to me
>

Here's a new series that includes those renames:
<https://lore.kernel.org/all/20230331110245.43527-1-me@crly.cz/>

It turns out however that the new dclk rates can't be set exactly as
requested without touching pll-video0*, tcon0 now therefore gets
reparented from pll-mipi to pll-video0-2x which, as it further turns
out, breaks DSI. While simply forbidding the video0-2x mux option seems
to me as the right way to go because there's not much use for it with
non-DSI interfaces either besides the opportunity to power pll-mipi
down, I'd like to run by you first.

Kind regards,
Roman

* As pll-mipi doesn't have CLK_SET_RATE_PARENT flag set, pll-video0
  retains its boot-time rate of 294 MHz set by sunxi-dw-hdmi driver
  in u-boot. Why 294 MHz (as opposed to the default rate of 297 MHz)?
  The driver actually asks for 297 MHz, clock_set_pll3 rounds it to
  294 MHz though because it limits itself to 6 MHz steps.