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Message-Id: <20230406194158.963352-6-cristian.ciocaltea@collabora.com>
Date: Thu, 6 Apr 2023 22:41:55 +0300
From: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
To: Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Heiko Stuebner <heiko@...ech.de>,
Bjorn Andersson <andersson@...nel.org>,
Joseph Chen <chenjh@...k-chips.com>,
Ezequiel Garcia <ezequiel@...guardiasur.com.ar>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
kernel@...labora.com
Subject: [PATCH v3 5/8] regulator: fan53555: Make use of the bit macros
For consistency and improved clarity, use BIT() and GENMASK() macros for
defining the bitfields inside the registers. No functional changes
intended.
While here, also fix DIE_{ID,REV} inconsistent indentation.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
---
drivers/regulator/fan53555.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c
index 68ebcd4ccef7..181e5eb00e7a 100644
--- a/drivers/regulator/fan53555.c
+++ b/drivers/regulator/fan53555.c
@@ -41,23 +41,23 @@
#define FAN53555_MONITOR 0x05
/* VSEL bit definitions */
-#define VSEL_BUCK_EN (1 << 7)
-#define VSEL_MODE (1 << 6)
+#define VSEL_BUCK_EN BIT(7)
+#define VSEL_MODE BIT(6)
/* Chip ID and Verison */
-#define DIE_ID 0x0F /* ID1 */
-#define DIE_REV 0x0F /* ID2 */
+#define DIE_ID 0x0F /* ID1 */
+#define DIE_REV 0x0F /* ID2 */
/* Control bit definitions */
-#define CTL_OUTPUT_DISCHG (1 << 7)
-#define CTL_SLEW_MASK (0x7 << 4)
-#define CTL_RESET (1 << 2)
+#define CTL_OUTPUT_DISCHG BIT(7)
+#define CTL_SLEW_MASK GENMASK(6, 4)
+#define CTL_RESET BIT(2)
#define CTL_MODE_VSEL0_MODE BIT(0)
#define CTL_MODE_VSEL1_MODE BIT(1)
#define FAN53555_NVOLTAGES 64 /* Numbers of voltages */
#define FAN53526_NVOLTAGES 128
-#define TCS_VSEL0_MODE (1 << 7)
-#define TCS_VSEL1_MODE (1 << 6)
+#define TCS_VSEL0_MODE BIT(7)
+#define TCS_VSEL1_MODE BIT(6)
#define TCS_SLEW_MASK GENMASK(4, 3)
--
2.40.0
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