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Date: Thu, 6 Apr 2023 16:13:10 -0400
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: Ian Rogers <irogers@...gle.com>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
Adrian Hunter <adrian.hunter@...el.com>,
Zhengjun Xing <zhengjun.xing@...ux.intel.com>,
linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org
Subject: Re: [PATCH v1 1/5] perf vendor events intel: Update free running
alderlake events
On 2023-04-06 2:46 p.m., Ian Rogers wrote:
> Fix the PMU name, event code and umask.
>
> These updates were generated by:
> https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
> with this PR:
> https://github.com/intel/perfmon/pull/66
>
> Signed-off-by: Ian Rogers <irogers@...gle.com>
> ---
> .../arch/x86/alderlake/uncore-memory.json | 16 ++++++++++++----
> .../arch/x86/alderlaken/uncore-memory.json | 16 ++++++++++++----
> 2 files changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
> index 2ccd9cf96957..ea25bb411f89 100644
> --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
> +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
> @@ -1,29 +1,37 @@
> [
> {
> "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).",
> + "EventCode": "0xff",
> "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
> "PerPkg": "1",
> "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).",
> - "Unit": "iMC"
> + "UMask": "0x20",
> + "Unit": "imc_free_running"
The imc_free_running will give the counter value for both imc0 and imc1.
I think we need "Unit": "imc_free_running_0" here. But I'm not sure if
the perf tool can handle it.
Thanks,
Kan
> },
> {
> "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
> + "EventCode": "0xff",
> "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
> "PerPkg": "1",
> - "Unit": "iMC"
> + "UMask": "0x30",
> + "Unit": "imc_free_running"
> },
> {
> "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).",
> + "EventCode": "0xff",
> "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
> "PerPkg": "1",
> "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).",
> - "Unit": "iMC"
> + "UMask": "0x20",
> + "Unit": "imc_free_running"
> },
> {
> "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
> + "EventCode": "0xff",
> "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
> "PerPkg": "1",
> - "Unit": "iMC"
> + "UMask": "0x30",
> + "Unit": "imc_free_running"
> },
> {
> "BriefDescription": "ACT command for a read request sent to DRAM",
> diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json
> index 2ccd9cf96957..ea25bb411f89 100644
> --- a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json
> +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json
> @@ -1,29 +1,37 @@
> [
> {
> "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).",
> + "EventCode": "0xff",
> "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
> "PerPkg": "1",
> "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).",
> - "Unit": "iMC"
> + "UMask": "0x20",
> + "Unit": "imc_free_running"
> },
> {
> "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
> + "EventCode": "0xff",
> "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
> "PerPkg": "1",
> - "Unit": "iMC"
> + "UMask": "0x30",
> + "Unit": "imc_free_running"
> },
> {
> "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).",
> + "EventCode": "0xff",
> "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
> "PerPkg": "1",
> "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).",
> - "Unit": "iMC"
> + "UMask": "0x20",
> + "Unit": "imc_free_running"
> },
> {
> "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
> + "EventCode": "0xff",
> "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
> "PerPkg": "1",
> - "Unit": "iMC"
> + "UMask": "0x30",
> + "Unit": "imc_free_running"
> },
> {
> "BriefDescription": "ACT command for a read request sent to DRAM",
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