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Message-ID: <ZC9cWnimsXNs8xqv@google.com>
Date: Thu, 6 Apr 2023 16:57:14 -0700
From: Sean Christopherson <seanjc@...gle.com>
To: Like Xu <like.xu.linux@...il.com>
Cc: Paolo Bonzini <pbonzini@...hat.com>, kvm@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 06/12] KVM: x86/pmu: Make part of the Intel v2 PMU MSRs
handling x86 generic
On Tue, Feb 14, 2023, Like Xu wrote:
> From: Like Xu <likexu@...cent.com>
>
> The AMD PerfMonV2 defines three registers similar to part of the Intel
Drop the "The", i.e. just "AMD PerfMonV2 defines ..."
> v2 PMU registers, including the GLOBAL_CTRL, GLOBAL_STATUS and
> GLOBAL_OVF_CTRL MSRs. For better code reuse, this specific part of
> the handling can be extracted to make it generic for X86 as a straight
> code movement.
State what the patch actually does, not what it could do, or what can be done.
> Specifically, move the kvm_pmu_set/get_msr() hanlders of GLOBAL_STATUS,
s/hanlders/handlers
> GLOBAL_CTRL, GLOBAL_OVF_CTRL defined by intel to generic pmu.c and
Intel
> remove the callback function .pmc_is_globally_enabled, which is very
> helpful to introduce the AMD PerfMonV2 code later.
>
> The new non-prefix pmc_is_globally_enabled() works well as legacy AMD
What prefix? It was pmc_is_globally_enabled() before and it's pmc_is_globally_enabled()
now?
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