lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230406103308.1280860-3-william.qiu@starfivetech.com>
Date:   Thu, 6 Apr 2023 18:33:08 +0800
From:   William Qiu <william.qiu@...rfivetech.com>
To:     <devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
CC:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor@...nel.org>,
        "Emil Renner Berthing" <kernel@...il.dk>,
        William Qiu <william.qiu@...rfivetech.com>
Subject: [PATCH v7 2/2] riscv: dts: starfive: jh7110: Add syscon nodes

Add stg_syscon/sys_syscon/aon_syscon nodes for JH7110 Soc.

Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..f271c3184d3a 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -353,6 +353,11 @@ i2c2: i2c@...50000 {
 			status = "disabled";
 		};

+		stg_syscon: syscon@...40000 {
+			compatible = "starfive,jh7110-stg-syscon", "syscon";
+			reg = <0x0 0x10240000 0x0 0x1000>;
+		};
+
 		uart3: serial@...00000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x12000000 0x0 0x10000>;
@@ -457,6 +462,11 @@ syscrg: clock-controller@...20000 {
 			#reset-cells = <1>;
 		};

+		sys_syscon: syscon@...30000 {
+			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
+			reg = <0x0 0x13030000 0x0 0x1000>;
+		};
+
 		sysgpio: pinctrl@...40000 {
 			compatible = "starfive,jh7110-sys-pinctrl";
 			reg = <0x0 0x13040000 0x0 0x10000>;
@@ -486,6 +496,11 @@ aoncrg: clock-controller@...00000 {
 			#reset-cells = <1>;
 		};

+		aon_syscon: syscon@...10000 {
+			compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd";
+			reg = <0x0 0x17010000 0x0 0x1000>;
+		};
+
 		aongpio: pinctrl@...20000 {
 			compatible = "starfive,jh7110-aon-pinctrl";
 			reg = <0x0 0x17020000 0x0 0x10000>;
--
2.34.1

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ