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Message-ID: <20230406102149.729726-6-nikolaos.pasaloukos@blaize.com>
Date: Thu, 6 Apr 2023 10:22:32 +0000
From: Niko Pasaloukos <nikolaos.pasaloukos@...ize.com>
To: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC: "soc@...nel.org" <soc@...nel.org>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"olof@...om.net" <olof@...om.net>,
"catalin.marinas@....com" <catalin.marinas@....com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
"sboyd@...nel.org" <sboyd@...nel.org>,
Niko Pasaloukos <nikolaos.pasaloukos@...ize.com>,
James Cowgill <james.cowgill@...ize.com>,
Matt Redfearn <matthew.redfearn@...ize.com>,
Neil Jones <neil.jones@...ize.com>
Subject: [PATCH 5/5] arm64: Add initial support for Blaize BLZP1600 CB2
Adds support for the Blaize CB2 development board based on
BLZP1600 SoC. This consists of a Carrier-Board and a SoM.
The blaize-blzp1600.dtsi is the common part for the SoC,
blaize-blzp1600-som.dtsi is the common part for the SoM and
blaize-blzp1600-som-cb2.dts is the board specific file.
Co-developed-by: James Cowgill <james.cowgill@...ize.com>
Signed-off-by: James Cowgill <james.cowgill@...ize.com>
Co-developed-by: Matt Redfearn <matt.redfearn@...ize.com>
Signed-off-by: Matt Redfearn <matt.redfearn@...ize.com>
Co-developed-by: Neil Jones <neil.jones@...ize.com>
Signed-off-by: Neil Jones <neil.jones@...ize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@...ize.com>
---
arch/arm64/Kconfig.platforms | 5 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/blaize/Makefile | 2 +
.../dts/blaize/blaize-blzp1600-som-cb.dtsi | 217 +++++
.../dts/blaize/blaize-blzp1600-som-cb2.dts | 103 ++
.../boot/dts/blaize/blaize-blzp1600-som.dtsi | 104 ++
.../boot/dts/blaize/blaize-blzp1600.dtsi | 894 ++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
8 files changed, 1327 insertions(+)
create mode 100644 arch/arm64/boot/dts/blaize/Makefile
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som-cb.dtsi
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som-cb2.dts
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 333d0af650d2..ab89cb7e557f 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -94,6 +94,11 @@ config ARCH_BITMAIN
help
This enables support for the Bitmain SoC Family.
+config ARCH_BLAIZE_BLZP1600
+ bool "Blaize BLZP1600 SoC Platforms"
+ help
+ This enables support for the Blaize BLZP1600 SoC family
+
config ARCH_EXYNOS
bool "ARMv8 based Samsung Exynos SoC family"
select COMMON_CLK_SAMSUNG
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 7b107fa7414b..d2fd6ab437ac 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += apm
subdir-y += apple
subdir-y += arm
subdir-y += bitmain
+subdir-y += blaize
subdir-y += broadcom
subdir-y += cavium
subdir-y += exynos
diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blaize/Makefile
new file mode 100644
index 000000000000..968c0d687897
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_BLAIZE_BLZP1600) += blaize-blzp1600-som-cb2.dtb
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som-cb.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som-cb.dtsi
new file mode 100644
index 000000000000..be09759f48f9
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som-cb.dtsi
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+#include "blaize-blzp1600-som.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ aliases {
+ ethernet = &gmac;
+ };
+
+ sound: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "BLZP1600-TLV320AIC3100";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "MIC1LP", "Microphone Jack",
+ "MIC1RP", "Microphone Jack",
+ "MIC1LP", "MICBIAS",
+ "MIC1RP", "MICBIAS",
+ "Headphone Jack", "HPL",
+ "Headphone Jack", "HPR";
+
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s_slave>;
+ };
+
+ sound0_master: simple-audio-card,codec {
+ sound-dai = <&audio_codec>;
+ clocks = <&scmi_clk BLZP1600_I2S_CODEC_CLK>;
+ system-clock-frequency = <12500000>;
+ /* board specific crystal/oscillator */
+ assigned-clocks = <&scmi_clk BLZP1600_SRC_I2S_CLK>;
+ assigned-clock-rates = <24576000>;
+ };
+ };
+
+ regulators {
+ vmmc_sd: regulator-sdio0-en {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc-reg-en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100000>;
+ };
+
+ vmmc_io: regulator-sdio0-io {
+ compatible = "regulator-gpio";
+ regulator-name = "mmc-reg-io";
+ regulator-ramp-delay = <10000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0 3300000 0x1>;
+ };
+ };
+};
+
+&canfd0 {
+ status = "okay";
+};
+
+&dsi_panel_0 {
+ reset-gpio = <&gpio0 9 GPIO_ACTIVE_LOW>;
+};
+
+&gmac {
+ status = "okay";
+ snps,reset-delays-us = <0 10000 50000>;
+ snps,reset-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_6_B_NIB>;
+ };
+ };
+};
+
+&gpio0 {
+ status = "okay";
+ gpio-line-names = "PERST_N", /* GPIO_0 */
+ "LM96063_ALERT_N", /* GPIO_1 */
+ "INA3221_PV", /* GPIO_2 */
+ "INA3221_CRIT", /* GPIO_3 */
+ "INA3221_WARN", /* GPIO_4 */
+ "INA3221_TC", /* GPIO_5 */
+ "QSPI0_RST_N", /* GPIO_6 */
+ "LM96063_TCRIT_N", /* GPIO_7 */
+ "DSI_TCH_INT", /* GPIO_8 */
+ "DSI_RST", /* GPIO_9 */
+ "DSI_BL", /* GPIO_10 */
+ "DSI_INT", /* GPIO_11 */
+ "ETH_RST", /* GPIO_12 */
+ "CSI0_RST", /* GPIO_13 */
+ "CSI0_PWDN", /* GPIO_14 */
+ "CSI1_RST", /* GPIO_15 */
+ "CSI1_PWDN", /* GPIO_16 */
+ "CSI2_RST", /* GPIO_17 */
+ "CSI2_PWDN", /* GPIO_18 */
+ "CSI3_RST", /* GPIO_19 */
+ "CSI3_PWDN", /* GPIO_20 */
+ "ADAC_RST", /* GPIO_21 */
+ "SD_SW_VDD", /* GPIO_22 */
+ "SD_PON_VDD", /* GPIO_23 */
+ "GPIO_EXP_INT", /* GPIO_24 */
+ "BOARD_ID_0", /* GPIO_25 */
+ "SDIO1_SW_VDD", /* GPIO_26 */
+ "SDIO1_PON_VDD", /* GPIO_27 */
+ "SDIO2_SW_VDD", /* GPIO_28 */
+ "SDIO2_PON_VDD", /* GPIO_29 */
+ "BOARD_ID_1", /* GPIO_30 */
+ "BOARD_ID_2"; /* GPIO_31 */
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ audio_codec: audio-codec@18 {
+ compatible = "ti,tlv320aic3100";
+ reg = <0x18>;
+ #sound-dai-cells = <0>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ reset-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ gpio_expander: gpio@74 {
+ compatible = "ti,tca9539";
+ reg = <0x74>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&i2s_master {
+ status = "okay";
+};
+
+&i2s_slave {
+ status = "okay";
+};
+
+&sd {
+ wp-inverted;
+ no-sdio;
+ no-mmc;
+ card-detect-delay = <200>;
+ vmmc-supply = <&vmmc_sd>;
+ vqmmc-supply = <&vmmc_io>;
+ status = "okay";
+};
+
+&sdio0 {
+ no-sd;
+ no-sdio;
+ non-removable;
+ wp-inverted;
+ status = "okay";
+ no-3-3-v;
+};
+
+&spim {
+ //spidev@2 {
+ // compatible = "spidev";
+ // spi-max-frequency = <100>;
+ // reg = <2>;
+ //};
+};
+
+&spis {
+ //status = "okay";
+ //
+ //slave {
+ // compatible = "spidev";
+ // status = "okay";
+ // spi-max-frequency = <100>;
+ //};
+};
+
+&usb3 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som-cb2.dts
new file mode 100644
index 000000000000..09925db3c58a
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som-cb2.dts
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "blaize-blzp1600-som-cb.dtsi"
+
+/ {
+ model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
+
+ compatible = "blaize,blzp1600-som-cb2", "blaize,blzp1600";
+
+ regulators {
+ vmmc_sdio1: regulator-sdio1-en {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc-sdio1-en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100000>;
+ };
+
+ vmmc_sdio1_io: regulator-sdio1-io {
+ compatible = "regulator-gpio";
+ regulator-name = "mmc-sdio1-io";
+ regulator-ramp-delay = <10000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0 3300000 0x1>;
+ };
+ };
+};
+
+&gpio_expander {
+ gpio-line-names = "RSP_PIN_7", /* GPIO_0 */
+ "RSP_PIN_11", /* GPIO_1 */
+ "RSP_PIN_13", /* GPIO_2 */
+ "RSP_PIN_15", /* GPIO_3 */
+ "RSP_PIN_27", /* GPIO_4 */
+ "RSP_PIN_29", /* GPIO_5 */
+ "RSP_PIN_31", /* GPIO_6 */
+ "RSP_PIN_33", /* GPIO_7 */
+ "RSP_PIN_37", /* GPIO_8 */
+ "RSP_PIN_16", /* GPIO_9 */
+ "RSP_PIN_18", /* GPIO_10 */
+ "RSP_PIN_22", /* GPIO_11 */
+ "RSP_PIN_28", /* GPIO_12 */
+ "RSP_PIN_32", /* GPIO_13 */
+ "RSP_PIN_36", /* GPIO_14 */
+ "TP31"; /* GPIO_15 */
+};
+
+&i2c3 {
+ gpio_expander_m2: gpio@75 {
+ compatible = "ti,tca9539";
+ reg = <0x75>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */
+ "M2_W_DIS2_N", /* GPIO_1 */
+ "M2_UART_WAKE_N", /* GPIO_2 */
+ "M2_COEX3", /* GPIO_3 */
+ "M2_COEX_RXD", /* GPIO_4 */
+ "M2_COEX_TXD", /* GPIO_5 */
+ "M2_VENDOR_PIN40", /* GPIO_6 */
+ "M2_VENDOR_PIN42", /* GPIO_7 */
+ "M2_VENDOR_PIN38", /* GPIO_8 */
+ "M2_SDIO_RST_N", /* GPIO_9 */
+ "M2_SDIO_WAKE_N", /* GPIO_10 */
+ "M2_PETN1", /* GPIO_11 */
+ "M2_PERP1", /* GPIO_12 */
+ "M2_PERN1", /* GPIO_13 */
+ "UIM_SWP", /* GPIO_14 */
+ "UART1_TO_RSP"; /* GPIO_15 */
+ };
+};
+
+&sdio1 {
+ no-mmc;
+ no-sd;
+ non-removable;
+ vmmc-supply = <&vmmc_sdio1>;
+ vqmmc-supply = <&vmmc_sdio1_io>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ //status = "okay";
+ keep-power-in-suspend;
+ no-3-3-v;
+ // Override bits 0-SDR50, 1-SDR104, 2-DDR50 to respect the dtb properties
+ sdhci-caps-mask = <0x7 0x0>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+
+ mwifiex: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
new file mode 100644
index 000000000000..39790ae19a2c
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+#include "blaize-blzp1600.dtsi"
+
+/ {
+ memory@...0 {
+ device_type = "memory";
+ reg = <0x0 0x00001000 0xfffff000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200";
+ };
+};
+
+&gsp {
+ blaize,power-limit-peak = <27001>; /* Power in mW */
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ hwmon-ina3221@40 {
+ compatible = "ti,ina3221";
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ input@0 {
+ reg = <0x0>;
+ label = "dual-rail1-1v1-1v8";
+ shunt-resistor-micro-ohms = <1000>;
+ };
+ input@1 {
+ reg = <0x1>;
+ label = "single-rail1-0v8";
+ shunt-resistor-micro-ohms = <25000>;
+ };
+ input@2 {
+ reg = <0x2>;
+ label = "dual-rail2-1v1-1v8";
+ shunt-resistor-micro-ohms = <1000>;
+ };
+ };
+
+ hwmon-lm96063@4c {
+ compatible = "national,lm96163";
+ reg = <0x4c>;
+ };
+};
+
+&spim {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <1000000>;
+ reg = <0>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fip@0 {
+ label = "fip";
+ reg = <0x0000000 0xe0000>;
+ read-only;
+ };
+
+ uboot-env@...00 {
+ label = "u-boot-env";
+ reg = <0xe0000 0x10000>;
+ };
+
+ dtb@...00 {
+ label = "dtb";
+ reg = <0xf0000 0x10000>;
+ };
+
+ image@...000 {
+ label = "linux";
+ reg = <0x100000 0x800000>;
+ };
+
+ rfs@...000 {
+ label = "rfs";
+ reg = <0x900000 0x3700000>;
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
new file mode 100644
index 000000000000..5641a95795dc
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
@@ -0,0 +1,894 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/blaize,blzp1600-reset.h>
+#include <dt-bindings/clock/blaize,blzp1600-clk.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0 0x0>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0 0x1>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = /* Physical Secure PPI */
+ <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ /* Physical Non-Secure PPI */
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ /* Hypervisor PPI */
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ /* Virtual PPI */
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ hwmon {
+ compatible = "blaize,blzp1600-hwmon";
+ clocks = <&scmi_clk BLZP1600_TSENSOR_CLK>;
+ resets = <&scmi_rst BLZP1600_TSENSOR_RST>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+
+ sram@0 {
+ /*
+ * On BLZP1600 there is no general purpose (non-secure) SRAM.
+ * A small DDR memory space has been reserved for general use.
+ */
+ compatible = "mmio-sram";
+ reg = <0x0 0x00000000 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x00000000 0x1000>;
+
+ /* SCMI reserved buffer space on DDR space */
+ scmi0_shm: scmi-sram@800 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x800 0x80>;
+ };
+ };
+
+ firmware {
+ scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82002000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+ shmem = <&scmi0_shm>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ scmi_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ spim: spi@...300000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x2 0x00300000 0x10000>;
+ clocks = <&scmi_clk BLZP1600_QSPI_CLK>,
+ <&scmi_clk BLZP1600_QSPI_PCLK>;
+ clock-names = "ssi_clk", "pclk";
+ resets = <&scmi_rst BLZP1600_QSPI_RST>,
+ <&scmi_rst BLZP1600_QSPI_PRST>;
+ reset-names = "spi", "pspi";
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ num-cs = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@...410000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2 0x00410000 0x20000>,
+ <0x2 0x00420000 0x20000>,
+ <0x2 0x00440000 0x20000>,
+ <0x2 0x00460000 0x20000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ public_soc_registers: syscon@...490000 {
+ compatible = "blaize,blzp1600-sys", "syscon";
+ reg = <0x2 0x00490000 0x5000>;
+ };
+
+ csitx0_dphy: csitx0-dphy@...492000 {
+ compatible = "samsung,ln14lpp-mipi-dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_SRC_XTAL_CLK>,
+ <&scmi_clk BLZP1600_SRC_CSID_CLK>;
+ clock-names = "pclk", "byte_clk";
+ samsung,syscon = <&public_soc_registers 0x2000>;
+ samsung,phy-master;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ dsi0_dphy: dsi0-dphy@...492030 {
+ compatible = "samsung,ln14lpp-mipi-dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_SRC_XTAL_CLK>,
+ <&scmi_clk BLZP1600_SRC_DSI_CLK>;
+ clock-names = "pclk", "byte_clk";
+ samsung,syscon = <&public_soc_registers 0x2030>;
+ samsung,phy-master;
+ #phy-cells = <0>;
+ resets = <&dsi 0>;
+ reset-names = "dphy-reset";
+ status = "disabled";
+ };
+
+ csirx0_dphy: csirx0-dphy@...492060 {
+ compatible = "samsung,ln14lpp-mipi-dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_SRC_XTAL_CLK>;
+ clock-names = "pclk";
+ samsung,syscon = <&public_soc_registers 0x2060>;
+ samsung,phy-slave;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ csirx1_dphy: csirx1-dphy@...492070 {
+ compatible = "samsung,ln14lpp-mipi-dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_SRC_XTAL_CLK>;
+ clock-names = "pclk";
+ samsung,syscon = <&public_soc_registers 0x2070>;
+ samsung,phy-slave;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ csirx2_dphy: csirx2-dphy@...492080 {
+ compatible = "samsung,ln14lpp-mipi-dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_SRC_XTAL_CLK>;
+ clock-names = "pclk";
+ samsung,syscon = <&public_soc_registers 0x2080>;
+ samsung,phy-slave;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ csirx3_dphy: csirx3-dphy@...492090 {
+ compatible = "samsung,ln14lpp-mipi-dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_SRC_XTAL_CLK>;
+ clock-names = "pclk";
+ samsung,syscon = <&public_soc_registers 0x2090>;
+ samsung,phy-slave;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@...4b0000 {
+ compatible = "vsi,wdt";
+ reg = <0x2 0x004b0000 0x1000>;
+ clocks = <&scmi_clk BLZP1600_NIC_HALF_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-sec = <10>;
+ };
+
+ gpio0: gpio@...4c0000 {
+ compatible = "vsi,apb-gpio-0.2";
+ reg = <0x2 0x004c0000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ uart0: serial@...4d0000 {
+ compatible = "ns16550a";
+ device_type = "serial";
+ reg = <0x2 0x004d0000 0x1000>;
+ clocks = <&scmi_clk BLZP1600_UART0_CLK>;
+ resets = <&scmi_rst BLZP1600_UART0_RST>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart1: serial@...4e0000 {
+ compatible = "ns16550a";
+ device_type = "serial";
+ reg = <0x2 0x004e0000 0x1000>;
+ clocks = <&scmi_clk BLZP1600_UART1_CLK>;
+ resets = <&scmi_rst BLZP1600_UART1_RST>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@...4f0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x004f0000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_I2C0_CLK>;
+ resets = <&scmi_rst BLZP1600_I2C0_RST>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&axi_dmac 5>, <&axi_dmac 0>;
+ dma-names = "tx", "rx";
+ snps,dma-mask = <64>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@...500000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00500000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_I2C1_CLK>;
+ resets = <&scmi_rst BLZP1600_I2C1_RST>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&axi_dmac 6>, <&axi_dmac 1>;
+ dma-names = "tx", "rx";
+ snps,dma-mask = <64>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@...510000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00510000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_I2C2_CLK>;
+ resets = <&scmi_rst BLZP1600_I2C2_RST>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&axi_dmac 7>, <&axi_dmac 2>;
+ dma-names = "tx", "rx";
+ snps,dma-mask = <64>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@...520000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00520000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_I2C3_CLK>;
+ resets = <&scmi_rst BLZP1600_I2C3_RST>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&axi_dmac 8>, <&axi_dmac 3>;
+ dma-names = "tx", "rx";
+ snps,dma-mask = <64>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@...530000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00530000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_I2C4_CLK>;
+ resets = <&scmi_rst BLZP1600_I2C4_RST>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&axi_dmac 9>, <&axi_dmac 4>;
+ dma-names = "tx", "rx";
+ snps,dma-mask = <64>;
+ status = "disabled";
+ };
+
+ arm_cc712: crypto@...550000 {
+ compatible = "arm,cryptocell-712-ree";
+ reg = <0x2 0x00550000 0x1000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 7>;
+ };
+
+ gsp: gsp@...5b0000 {
+ compatible = "blaize,blzp1600-gsp";
+ reg = <0x2 0x005b0000 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&scmi_clk BLZP1600_GSP_CLK>;
+ clock-names = "gsp_ref_clk";
+ resets = <&scmi_rst BLZP1600_GSP_RST>;
+ reset-names = "gsp_rst";
+ };
+
+ gmac: ethernet@...640000 {
+ compatible = "snps,dwmac";
+ reg = <0x2 0x640000 0x8000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <4096>;
+ max-frame-size = <2030>;
+ clocks = <&scmi_clk BLZP1600_ETH_MAC_CLK>,
+ <&scmi_clk BLZP1600_ETH_MAC_M_CLK>;
+ clock-names = "stmmaceth", "pclk";
+ resets = <&scmi_rst BLZP1600_ETH_MAC_RST>;
+ reset-names = "stmmaceth";
+ snps,pbl = <2>; // Maximum Burst Length 16.
+ snps,axi-config = <&stmmac_axi_setup>;
+ status = "disabled";
+ };
+
+ video_encoder: video-encoder@...650000 {
+ compatible = "blaize,blzp1600-encoder", "vsi,vc8000e";
+ reg = <0x2 0x650000 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "encoder";
+ clocks = <&scmi_clk BLZP1600_VIDEO_E_CLK>,
+ <&scmi_clk BLZP1600_NIC_CLK>,
+ <&scmi_clk BLZP1600_NIC_HALF_CLK>;
+ clock-names = "core", "axi", "apb";
+ resets = <&scmi_rst BLZP1600_VIDEO_E_RST>,
+ <&scmi_rst BLZP1600_VIDEO_E_REORDER_RST>;
+ };
+
+ video_decoder: video-decoder@...660000 {
+ compatible = "blaize,blzp1600-decoder", "vsi,vc8000d";
+ reg = <0x2 0x00660000 0x800>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "decoder", "decoder_l2";
+ clocks = <&scmi_clk BLZP1600_VIDEO_D_CLK>,
+ <&scmi_clk BLZP1600_NIC_CLK>,
+ <&scmi_clk BLZP1600_NIC_HALF_CLK>;
+ clock-names = "core", "axi", "apb";
+ resets = <&scmi_rst BLZP1600_VIDEO_D_RST>,
+ <&scmi_rst BLZP1600_VIDEO_D_REORDER_RST>,
+ <&scmi_rst BLZP1600_VIDEO_D_L2_RST>;
+ };
+
+ dpi_dma: dpi-dma@...670000 {
+ compatible = "blaize,blzp1600-drm-dma";
+ reg = <0x2 0x00670000 0x1000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
+ resets = <&scmi_rst BLZP1600_DSI_VDMA_RST>;
+ reset-names = "dpi_dma_rst";
+ clocks = <&scmi_clk BLZP1600_DSI_VDMA_CLK>;
+ clock-names = "dpi_dma_clk";
+ status = "disabled";
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
+
+ csirx0_vdma: csi-rx-vdma@...680000 {
+ compatible = "blaize,csirx-vdma-blzp1600";
+ reg = <0x2 0x00680000 0x1000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&scmi_clk BLZP1600_CSI0_VDMA_CLK>;
+ clock-names = "dma_clk";
+ resets = <&scmi_rst BLZP1600_CSI0_VDMA_RST>;
+
+ status = "disabled";
+ port@0 {
+ csi0_rx_in: endpoint {
+ remote-endpoint = <&csi0_out>;
+ };
+ };
+ };
+
+ csirx1_vdma: csi-rx-vdma@...690000 {
+ compatible = "blaize,csirx-vdma-blzp1600";
+ reg = <0x2 0x00690000 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&scmi_clk BLZP1600_CSI1_VDMA_CLK>;
+ clock-names = "dma_clk";
+ resets = <&scmi_rst BLZP1600_CSI1_VDMA_RST>;
+
+ status = "disabled";
+ port@0 {
+ csi1_rx_in: endpoint {
+ remote-endpoint = <&csi1_out>;
+ };
+ };
+ };
+
+ csirx2_vdma: csi-rx-vdma@...6a0000 {
+ compatible = "blaize,csirx-vdma-blzp1600";
+ reg = <0x2 0x006a0000 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&scmi_clk BLZP1600_CSI2_VDMA_CLK>;
+ clock-names = "dma_clk";
+ resets = <&scmi_rst BLZP1600_CSI2_VDMA_RST>;
+
+ status = "disabled";
+ port@0 {
+ csi2_rx_in: endpoint {
+ remote-endpoint = <&csi2_out>;
+ };
+ };
+ };
+
+ csirx3_vdma: csi-rx-vdma@...6b0000 {
+ compatible = "blaize,csirx-vdma-blzp1600";
+ reg = <0x2 0x006b0000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&scmi_clk BLZP1600_CSI3_VDMA_CLK>;
+ clock-names = "dma_clk";
+ resets = <&scmi_rst BLZP1600_CSI3_VDMA_RST>;
+
+ status = "disabled";
+ port@0 {
+ csi3_rx_in: endpoint {
+ remote-endpoint = <&csi3_out>;
+ };
+ };
+ };
+
+ csitx0_vdma: csi-tx-vdma@...6c0000 {
+ compatible = "blaize,csitx-vdma-blzp1600";
+ reg = <0x2 0x006c0000 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&scmi_clk BLZP1600_CSID_VDMA_CLK>;
+ clock-names = "dma_clk";
+ resets = <&scmi_rst BLZP1600_CSID_VDMA_RST>;
+
+ status = "disabled";
+ port {
+ csid_tx_out: endpoint {
+ remote-endpoint = <&csid_in>;
+ };
+ };
+ };
+
+ csirx0: csi-rx@...6e0000 {
+ compatible = "snps,mipi-csi2h";
+ reg = <0x2 0x006e0000 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_CSI0_CTRL_CLK>,
+ <&scmi_clk BLZP1600_CSI0_VDMA_CLK>;
+ clock-names = "csi2", "pix";
+ resets = <&scmi_rst BLZP1600_CSI0_CTRL_RST>;
+ snps,cut-through-mode;
+ phys = <&csirx0_dphy>;
+ phy-names = "dphy";
+
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+ csi0_in: endpoint {
+ // board specific
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ csi0_out: endpoint {
+ remote-endpoint = <&csi0_rx_in>;
+ };
+ };
+ };
+
+ csirx1: csi-rx@...6f0000 {
+ compatible = "snps,mipi-csi2h";
+ reg = <0x2 0x006f0000 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_CSI1_CTRL_CLK>,
+ <&scmi_clk BLZP1600_CSI1_VDMA_CLK>;
+ clock-names = "csi2", "pix";
+ resets = <&scmi_rst BLZP1600_CSI1_CTRL_RST>;
+ snps,cut-through-mode;
+ phys = <&csirx1_dphy>;
+ phy-names = "dphy";
+
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+ csi1_in: endpoint {
+ // board specific
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ csi1_out: endpoint {
+ remote-endpoint = <&csi1_rx_in>;
+ };
+ };
+ };
+
+ csirx2: csi-rx@...700000 {
+ compatible = "snps,mipi-csi2h";
+ reg = <0x2 0x00700000 0x1000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_CSI2_CTRL_CLK>,
+ <&scmi_clk BLZP1600_CSI2_VDMA_CLK>;
+ clock-names = "csi2", "pix";
+ resets = <&scmi_rst BLZP1600_CSI2_CTRL_RST>;
+ snps,cut-through-mode;
+ phys = <&csirx2_dphy>;
+ phy-names = "dphy";
+
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+ csi2_in: endpoint {
+ // board specific
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ csi2_out: endpoint {
+ remote-endpoint = <&csi2_rx_in>;
+ };
+ };
+ };
+
+ csirx3: csi-rx@...710000 {
+ compatible = "snps,mipi-csi2h";
+ reg = <0x2 0x00710000 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_CSI3_CTRL_CLK>,
+ <&scmi_clk BLZP1600_CSI3_VDMA_CLK>;
+ clock-names = "csi2", "pix";
+ resets = <&scmi_rst BLZP1600_CSI3_CTRL_RST>;
+ snps,cut-through-mode;
+ phys = <&csirx3_dphy>;
+ phy-names = "dphy";
+
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+ csi3_in: endpoint {
+ // board specific
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ csi3_out: endpoint {
+ remote-endpoint = <&csi3_rx_in>;
+ };
+ };
+ };
+
+ dsi: dsi@...6d0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "blaize,blzp1600-drm-dsi";
+ reg = <0x2 0x006d0000 0x1000>;
+ clocks = <&scmi_clk BLZP1600_DSI_CTRL_CLK>,
+ <&scmi_clk BLZP1600_SRC_XTAL_CLK>,
+ <&scmi_clk BLZP1600_DSI_VDMA_CLK>;
+ clock-names = "pclk", "ref", "dpipclk";
+ resets = <&scmi_rst BLZP1600_DSI_CTRL_RST>;
+ reset-names = "dsi";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
+ phys = <&dsi0_dphy>;
+ phy-names = "dphy";
+ #reset-cells = <1>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* 0 for input port */
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+ /* 1 for output port */
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ //remote-endpoint = <&dsi_display_in>;
+ };
+ };
+ };
+
+ dsi_panel_0: dsi-panel@0 {
+ reg = <0>; /* dsi virtual channel (0..3) */
+ status = "disabled";
+ };
+ };
+
+ csitx0: csi-tx@...720000 {
+ compatible = "snps,mipi-csi2d";
+ reg = <0x2 0x00720000 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_CSID_CTRL_CLK>,
+ <&scmi_clk BLZP1600_CSID_VDMA_CLK>;
+ clock-names = "pclk", "pix";
+ resets = <&scmi_rst BLZP1600_CSID_CTRL_RST>;
+ snps,cut-through-mode;
+ snps,master;
+ phys = <&csitx0_dphy>;
+ phy-names = "dphy";
+
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+ csid_in: endpoint {
+ remote-endpoint = <&csid_tx_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ csid_out: endpoint {
+ /* Board must set data-lanes */
+ bus-type = <0>;
+ };
+ };
+ };
+
+ i2s_master: i2s@...730000 {
+ compatible = "snps,designware-i2s";
+ reg = <0x2 0x00730000 0x1000>;
+ #sound-dai-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_I2S_MASTER_CLK>,
+ <&scmi_clk BLZP1600_I2S_TX_CLK>;
+ clock-names = "i2sclk", "i2s_pclk";
+ resets = <&scmi_rst BLZP1600_I2S_TX_RST>;
+ dmas = <&axi_dmac 13>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
+ i2s_slave: i2s@...740000 {
+ compatible = "snps,designware-i2s";
+ reg = <0x2 0x00740000 0x1000>;
+ #sound-dai-cells = <0>;
+ clocks = <&scmi_clk BLZP1600_I2S_RX_CLK>;
+ clock-names = "i2s_pclk";
+ resets = <&scmi_rst BLZP1600_I2S_RX_RST>;
+ dmas = <&axi_dmac 12>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ axi_dmac: dma-controller@...750000 {
+ compatible = "snps,axi-dma-1.02a";
+ reg = <0x2 0x00750000 0x10000>;
+ clocks = <&scmi_clk BLZP1600_DMA_CLK>,
+ <&scmi_clk BLZP1600_NIC_HALF_CLK>;
+ clock-names = "core-clk", "cfgr-clk";
+ resets = <&scmi_rst BLZP1600_DMA_RST>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <16>;
+ snps,dma-masters = <1>;
+ snps,data-width = <4>;
+ snps,block-size = <8192 8192 8192 8192
+ 8192 8192 8192 8192
+ 8192 8192 8192 8192
+ 8192 8192 8192 8192>;
+ snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+ snps,axi-max-burst-len = <16>;
+ snps,no-mem-to-mem-trans;
+ snps,dev-to-mem-trans;
+ snps,dma-cyclic;
+ snps,max-supported-channels = <16>;
+ #dma-cells = <1>;
+ };
+
+ sd: sdhci@...760000 {
+ compatible = "blaize,blzp1600-sdhci";
+ reg = <0x2 0x00760000 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_NIC_HALF_CLK>,
+ <&scmi_clk BLZP1600_SD_CARD_CLK>;
+ clock-names = "core", "bus";
+ resets = <&scmi_rst BLZP1600_SD_CARD_RST>;
+ fifo-depth = <8>;
+ bus-width = <4>;
+ blaize,syscon = <&public_soc_registers 0x4000>;
+ status = "disabled";
+ };
+
+ canfd0: canfd@...770000 {
+ compatible = "fraunhofer,canfd";
+ reg = <0x2 0x00770000 0x10000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_CAN0_CLK>;
+ clock-names = "can";
+ resets = <&scmi_rst BLZP1600_CAN0_RST>;
+ reset-names = "can";
+ status = "disabled";
+ };
+
+ canfd1: canfd@...780000 {
+ compatible = "fraunhofer,canfd";
+ reg = <0x2 0x00780000 0x10000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_CAN1_CLK>;
+ clock-names = "can";
+ resets = <&scmi_rst BLZP1600_CAN1_RST>;
+ reset-names = "can";
+ status = "disabled";
+ };
+
+ canfd2: canfd@...790000 {
+ compatible = "fraunhofer,canfd";
+ reg = <0x2 0x00790000 0x10000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_CAN2_CLK>;
+ clock-names = "can";
+ resets = <&scmi_rst BLZP1600_CAN2_RST>;
+ reset-names = "can";
+ status = "disabled";
+ };
+
+ sdio0: sdhci@...7a0000 {
+ compatible = "blaize,blzp1600-sdhci";
+ reg = <0x2 0x007a0000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_NIC_HALF_CLK>,
+ <&scmi_clk BLZP1600_SDIO0_CLK>;
+ clock-names = "core", "bus";
+ resets = <&scmi_rst BLZP1600_SDIO0_RST>;
+ fifo-depth = <8>;
+ bus-width = <4>;
+ blaize,syscon = <&public_soc_registers 0x4100>;
+ status = "disabled";
+ };
+
+ sdio1: sdhci@...7b0000 {
+ compatible = "blaize,blzp1600-sdhci";
+ reg = <0x2 0x007b0000 0x1000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_NIC_HALF_CLK>,
+ <&scmi_clk BLZP1600_SDIO1_CLK>;
+ clock-names = "core", "bus";
+ resets = <&scmi_rst BLZP1600_SDIO1_RST>;
+ fifo-depth = <8>;
+ bus-width = <4>;
+ blaize,syscon = <&public_soc_registers 0x4200>;
+ status = "disabled";
+ };
+
+ sdio2: sdhci@...7c0000 {
+ compatible = "blaize,blzp1600-sdhci";
+ reg = <0x2 0x007c0000 0x1000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_NIC_HALF_CLK>,
+ <&scmi_clk BLZP1600_SDIO2_CLK>;
+ clock-names = "core", "bus";
+ resets = <&scmi_rst BLZP1600_SDIO2_RST>;
+ fifo-depth = <8>;
+ bus-width = <4>;
+ blaize,syscon = <&public_soc_registers 0x4300>;
+ status = "disabled";
+ };
+
+ spis: spi@...7d0000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x2 0x007d0000 0x10000>;
+ clocks = <&scmi_clk BLZP1600_SPIS_CLK>,
+ <&scmi_clk BLZP1600_SPIS_PCLK>;
+ clock-names = "ssi_clk", "pclk";
+ resets = <&scmi_rst BLZP1600_SPIS_RST>,
+ <&scmi_rst BLZP1600_SPIS_PRST>;
+ reset-names = "spi", "pspi";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ spi-slave;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ usb3: usb3@...840000 {
+ compatible = "blaize,blzp1600-dwc3";
+ reg = <0x2 0x00840000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&scmi_clk BLZP1600_USB_PHY_CLK>;
+ clock-names = "phy_clk";
+ resets = <&scmi_rst BLZP1600_USB_PHY_RST>;
+ reset-names = "phy_rst";
+ status = "disabled";
+
+ dwc3: usb@...840000 {
+ compatible = "snps,dwc3";
+ reg = <0x2 0x00840000 0x10000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk BLZP1600_SRC_XTAL_CLK>,
+ <&scmi_clk BLZP1600_USB_CLK>,
+ <&scmi_clk BLZP1600_SRC_XTAL_CLK>;
+ clock-names = "ref", "bus_early", "suspend";
+ resets = <&scmi_rst BLZP1600_USB_RST>;
+ dr_mode = "host";
+ snps,dis-ref-clk-sof-quirk;
+ phy_type = "utmi_wide";
+ };
+ };
+ };
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 851e8f9be06d..6eab5c65476e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -39,6 +39,7 @@ CONFIG_ARCH_BCM2835=y
CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BCM_IPROC=y
CONFIG_ARCH_BERLIN=y
+CONFIG_ARCH_BLAIZE_BLZP1600=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_K3=y
--
2.25.1
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