linux-kernel - [PATCH V2] KVM: x86/pmu: Disable vPMU if EVENTSEL

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Message-Id: <20230407085646.24809-1-likexu@tencent.com>
Date:   Fri,  7 Apr 2023 16:56:46 +0800
From:   Like Xu <like.xu.linux@...il.com>
To:     Sean Christopherson <seanjc@...gle.com>
Cc:     Paolo Bonzini <pbonzini@...hat.com>, kvm@...r.kernel.org,
        linux-kernel@...r.kernel.org, Ravi Bangoria <ravi.bangoria@....com>
Subject: [PATCH V2] KVM: x86/pmu: Disable vPMU if EVENTSEL_GUESTONLY bit doesn't exist

From: Like Xu <likexu@...cent.com>

Unlike Intel's MSR atomic_switch mechanism, AMD supports guest pmu
basic counter feature by setting the GUESTONLY bit on the host, so the
presence or absence of this bit determines whether vPMU is emulatable
(e.g. in nested virtualization). Since on AMD, writing reserved bits of
EVENTSEL register does not bring #GP, KVM needs to update the global
enable_pmu value by checking the persistence of this GUESTONLY bit.

Cc: Ravi Bangoria <ravi.bangoria@....com>
Signed-off-by: Like Xu <likexu@...cent.com>
---
V1:
https://lore.kernel.org/kvm/20230307113819.34089-1-likexu@tencent.com
V1 -> V2 Changelog:
- Preemption needs to be disabled to ensure a stable CPU; (Sean)
- KVM should be restoring the original value too; (Sean)
- Disable vPMU once guest_only mode is not supported; (Sean)
- Appreciate any better way to probe for GUESTONLY support;

 arch/x86/kvm/svm/svm.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 7584eb85410b..1ab885596510 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -4884,6 +4884,20 @@ static __init void svm_adjust_mmio_mask(void)
 	kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
 }
 
+static __init bool pmu_has_guestonly_mode(void)
+{
+	u64 original, value;
+
+	preempt_disable();
+	rdmsrl(MSR_F15H_PERF_CTL0, original);
+	wrmsrl(MSR_F15H_PERF_CTL0, AMD64_EVENTSEL_GUESTONLY);
+	rdmsrl(MSR_F15H_PERF_CTL0, value);
+	wrmsrl(MSR_F15H_PERF_CTL0, original);
+	preempt_enable();
+
+	return value == AMD64_EVENTSEL_GUESTONLY;
+}
+
 static __init void svm_set_cpu_caps(void)
 {
 	kvm_set_cpu_caps();
@@ -4928,6 +4942,9 @@ static __init void svm_set_cpu_caps(void)
 	    boot_cpu_has(X86_FEATURE_AMD_SSBD))
 		kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 
+	/* Probe for AMD64_EVENTSEL_GUESTONLY support */
+	enable_pmu &= pmu_has_guestonly_mode();
+
 	/* AMD PMU PERFCTR_CORE CPUID */
 	if (enable_pmu && boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
 		kvm_cpu_cap_set(X86_FEATURE_PERFCTR_CORE);

base-commit: 649bccd7fac98225525c79cf4b1cecc4bafdfc54
-- 
2.40.0