linux-kernel - Re: [PATCH V3 3/4] clk: imx: imx8mp: Add LDB root clock

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Date:   Sun, 9 Apr 2023 16:35:59 +0300
From:   Abel Vesa <abel.vesa@...aro.org>
To:     "Peng Fan (OSS)" <peng.fan@....nxp.com>
Cc:     abelvesa@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
        shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de,
        festevam@...il.com, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, linux-imx@....com,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        Liu Ying <victor.liu@....com>, Sandor Yu <Sandor.yu@....com>,
        Dong Aisheng <aisheng.dong@....com>,
        Peng Fan <peng.fan@....com>
Subject: Re: [PATCH V3 3/4] clk: imx: imx8mp: Add LDB root clock

On 23-04-03 17:46:32, Peng Fan (OSS) wrote:
> From: Liu Ying <victor.liu@....com>
> 
> This patch adds "media_ldb_root_clk" clock for
> the LDB in the MEDIAMIX subsystem.
> 
> Reviewed-by: Sandor Yu <Sandor.yu@....com>
> Signed-off-by: Liu Ying <victor.liu@....com>
> Signed-off-by: Dong Aisheng <aisheng.dong@....com>
> Signed-off-by: Peng Fan <peng.fan@....com>

Reviewed-by: Abel Vesa <abel.vesa@...aro.org>

> ---
> 
> V3:
>  None
> V2:
>  Seperate binding
> 
>  drivers/clk/imx/clk-imx8mp.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 4a0f1b739fd4..8dcaeb213277 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -696,6 +696,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media);
>  	hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media);
>  	hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] = imx_clk_hw_gate2_shared2("media_mipi_phy1_ref_root", "media_mipi_phy1_ref", ccm_base + 0x45d0, 0, &share_count_media);
> +	hws[IMX8MP_CLK_MEDIA_LDB_ROOT] = imx_clk_hw_gate2_shared2("media_ldb_root_clk", "media_ldb", ccm_base + 0x45d0, 0, &share_count_media);
>  	hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media);
>  
>  	hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
> -- 
> 2.37.1
>