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Message-ID: <ZDLBUsQ+YyWi98Hm@linaro.org>
Date: Sun, 9 Apr 2023 16:44:50 +0300
From: Abel Vesa <abel.vesa@...aro.org>
To: "Peng Fan (OSS)" <peng.fan@....nxp.com>
Cc: abelvesa@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de,
festevam@...il.com, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, linux-imx@....com,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Peng Fan <peng.fan@....com>
Subject: Re: [PATCH V3 2/7] clk: imx: fracn-gppll: disable hardware select
control
On 23-04-03 17:52:55, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@....com>
>
> When programming PLL, should disable Hardware control select to make PLL
> controlled by register, not hardware inputs through OSCPLL.
>
> Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
> Signed-off-by: Peng Fan <peng.fan@....com>
Reviewed-by: Abel Vesa <abel.vesa@...aro.org>
> ---
> drivers/clk/imx/clk-fracn-gppll.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
> index ec50c41e2a4c..f6674110a88e 100644
> --- a/drivers/clk/imx/clk-fracn-gppll.c
> +++ b/drivers/clk/imx/clk-fracn-gppll.c
> @@ -15,6 +15,7 @@
> #include "clk.h"
>
> #define PLL_CTRL 0x0
> +#define HW_CTRL_SEL BIT(16)
> #define CLKMUX_BYPASS BIT(2)
> #define CLKMUX_EN BIT(1)
> #define POWERUP_MASK BIT(0)
> @@ -193,6 +194,11 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate,
>
> rate = imx_get_pll_settings(pll, drate);
>
> + /* Hardware control select disable. PLL is control by register */
> + tmp = readl_relaxed(pll->base + PLL_CTRL);
> + tmp &= ~HW_CTRL_SEL;
> + writel_relaxed(tmp, pll->base + PLL_CTRL);
> +
> /* Disable output */
> tmp = readl_relaxed(pll->base + PLL_CTRL);
> tmp &= ~CLKMUX_EN;
> --
> 2.37.1
>
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