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Message-ID: <20230410073752.39506-4-jiajie.ho@starfivetech.com>
Date: Mon, 10 Apr 2023 15:37:51 +0800
From: Jia Jie Ho <jiajie.ho@...rfivetech.com>
To: Herbert Xu <herbert@...dor.apana.org.au>,
"David S . Miller" <davem@...emloft.net>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Emil Renner Berthing <kernel@...il.dk>,
Conor Dooley <conor.dooley@...rochip.com>
CC: <linux-crypto@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
Subject: [PATCH v4 3/4] riscv: dts: starfive: Add crypto and DMA node for VisionFive 2
Add StarFive cryptographic module and dedicated DMA controller node to
VisionFive 2 SoCs.
Co-developed-by: Huan Feng <huan.feng@...rfivetech.com>
Signed-off-by: Huan Feng <huan.feng@...rfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@...rfivetech.com>
Acked-by: Palmer Dabbelt <palmer@...osinc.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 28 ++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4ac159d79d66..591abe57ec31 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -455,5 +455,33 @@ uart5: serial@...20000 {
reg-shift = <2>;
status = "disabled";
};
+
+ sdma: dma@...08000 {
+ compatible = "arm,pl080", "arm,primecell";
+ arm,primecell-periphid = <0x00041080>;
+ reg = <0x0 0x16008000 0x0 0x4000>;
+ interrupts = <29>;
+ clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+ <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+ clock-names = "hclk", "apb_pclk";
+ resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+ lli-bus-interface-ahb1;
+ mem-bus-interface-ahb1;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+ };
+
+ crypto: crypto@...00000 {
+ compatible = "starfive,jh7110-crypto";
+ reg = <0x0 0x16000000 0x0 0x4000>;
+ clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+ <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+ clock-names = "hclk", "ahb";
+ interrupts = <28>;
+ resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+ dmas = <&sdma 1 2>, <&sdma 0 2>;
+ dma-names = "tx", "rx";
+ };
};
};
--
2.25.1
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