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Message-ID: <f568fd917bb8789fcef4206e256ef045176605e2.camel@xry111.site>
Date: Mon, 10 Apr 2023 22:37:56 +0800
From: Xi Ruoyao <xry111@...111.site>
To: Rui Wang <wangrui@...ngson.cn>
Cc: Huacai Chen <chenhuacai@...nel.org>,
WANG Xuerui <kernel@...0n.name>, loongarch@...ts.linux.dev,
linux-kernel@...r.kernel.org, loongson-kernel@...ts.loongnix.cn
Subject: Re: [PATCH] LoongArch: Improve memory ops
On Mon, 2023-04-10 at 22:19 +0800, Rui Wang wrote:
> On Mon, Apr 10, 2023 at 8:20 PM Xi Ruoyao <xry111@...111.site> wrote:
> >
> > On Mon, 2023-04-10 at 19:57 +0800, WANG rui wrote:
> > > + /* align up address */
> > > + andi t1, a0, 7
> > > + sub.d a0, a0, t1
> >
> > bstrins.d a0, zero, 2, 0
> >
> > Likewise for other aligning operations if the temporary is not used.
>
> I think we're on the same page. I had previously tested this on the
> user-space version[1], but it's not a performance-critical area.
The point is "if you can reduce one instruction and one register usage
with no harm, why not do it?" :)
AFAIK bstrins.d should be available on all 64-bit LoongArch CPUs.
--
Xi Ruoyao <xry111@...111.site>
School of Aerospace Science and Technology, Xidian University
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