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Message-Id: <20230411165919.23955-2-jim2101024@gmail.com>
Date: Tue, 11 Apr 2023 12:59:16 -0400
From: Jim Quinlan <jim2101024@...il.com>
To: linux-pci@...r.kernel.org,
Nicolas Saenz Julienne <nsaenz@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Cyril Brulebois <kibi@...ian.org>,
Phil Elwell <phil@...pberrypi.com>,
bcm-kernel-feedback-list@...adcom.com, jim2101024@...il.com,
james.quinlan@...adcom.com
Cc: Florian Fainelli <f.fainelli@...il.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-kernel@...ts.infradead.org (moderated list:BROADCOM BCM7XXX
ARM ARCHITECTURE),
linux-rpi-kernel@...ts.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
DEVICE TREE BINDINGS), linux-kernel@...r.kernel.org (open list)
Subject: [PATCH v2 1/3] dt-bindings: PCI: brcmstb: Add two optional props
Regarding "brcm,enable-l1ss":
The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
requires the driver probe() to deliberately place the HW one of three
CLKREQ# modes:
(a) CLKREQ# driven by the RC unconditionally
(b) CLKREQ# driven by the EP for ASPM L0s, L1
(c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
The HW+driver can tell the difference between downstream devices that
need (a) and (b), but does not know when to configure (c). Further, the
HW may cause a CPU abort on boot if guesses wrong regarding the need for
(c). So we introduce the boolean "brcm,enable-l1ss" property to indicate
that (c) is desired. Setting this property only makes sense when the
downstream device is L1SS-capable and the OS is configured to activate
this mode (e.g. policy==superpowersave).
This property is already present in the Raspian version of Linux, but the
upstream driver implementaion that will follow adds more details and
discerns between (a) and (b).
Regarding "brcm,completion-timeout-us"
Our HW will cause a CPU abort if the L1SS exit time is longer than the
PCIe transaction completion abort timeout. We've been asked to make this
configurable, so we are introducing "brcm,completion-timeout-us".
Signed-off-by: Jim Quinlan <jim2101024@...il.com>
---
.../devicetree/bindings/pci/brcm,stb-pcie.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 7e15aae7d69e..f7fc2f6561bb 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -64,6 +64,22 @@ properties:
aspm-no-l0s: true
+ brcm,enable-l1ss:
+ description: Indicates that PCIe L1SS power savings
+ are desired, the downstream device is L1SS-capable, and the
+ OS has been configured to enable this mode. Note that when
+ in this mode, this particular HW may not meet the requirement
+ that requires CLKREQ# assertion to clock active to be
+ within 400ns.
+ type: boolean
+
+ brcm,completion-timeout-us:
+ description: Number of microseconds before PCI transaction
+ completion timeout abort is signalled.
+ minimum: 16
+ default: 1000000
+ maximum: 19884107
+
brcm,scb-sizes:
description: u64 giving the 64bit PCIe memory
viewport size of a memory controller. There may be up to
--
2.17.1
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