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Message-Id: <20230411100346.299768-2-biju.das.jz@bp.renesas.com>
Date: Tue, 11 Apr 2023 11:03:39 +0100
From: Biju Das <biju.das.jz@...renesas.com>
To: Rob Herring <robh+dt@...nel.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Biju Das <biju.das.jz@...renesas.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Magnus Damm <magnus.damm@...il.com>,
linux-renesas-soc@...r.kernel.org, linux-media@...r.kernel.org,
dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH v2 1/8] arm64: dts: renesas: r9a07g044: Add fcpvd node
Add fcpvd node to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
---
v1->v2:
* Added Rb tag from Geert.
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 487536696d90..e90c517077ab 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -618,6 +618,18 @@ sbc: spi@...60000 {
status = "disabled";
};
+ fcpvd: fcp@...80000 {
+ compatible = "renesas,r9a07g044-fcpvd",
+ "renesas,fcpv";
+ reg = <0 0x10880000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_LCDC_RESET_N>;
+ };
+
cpg: clock-controller@...10000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0 0x11010000 0 0x10000>;
--
2.25.1
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