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Message-Id: <20230411100346.299768-6-biju.das.jz@bp.renesas.com>
Date: Tue, 11 Apr 2023 11:03:43 +0100
From: Biju Das <biju.das.jz@...renesas.com>
To: Rob Herring <robh+dt@...nel.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Biju Das <biju.das.jz@...renesas.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Magnus Damm <magnus.damm@...il.com>,
linux-renesas-soc@...r.kernel.org, linux-media@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH v2 5/8] arm64: dts: renesas: r9a07g044: Add DSI node
Add DSI node to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
---
v1->v2:
* Added Rb tag from Geert.
* Reorder the patch based on the module fcpvd, vspd and then DSI
for both RZ/G2L and RZ/V2L.
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 7698752742df..23bd28dd4d95 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -618,6 +618,34 @@ sbc: spi@...60000 {
status = "disabled";
};
+ dsi: dsi@...50000 {
+ compatible = "renesas,r9a07g044-mipi-dsi",
+ "renesas,rzg2l-mipi-dsi";
+ reg = <0 0x10850000 0 0x20000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "seq0", "seq1", "vin1", "rcv",
+ "ferr", "ppi", "debug";
+ clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
+ <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
+ <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
+ <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
+ <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
+ <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
+ clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
+ resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
+ <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
+ <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
+ reset-names = "rst", "arst", "prst";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
vspd: vsp@...70000 {
compatible = "renesas,r9a07g044-vsp2";
reg = <0 0x10870000 0 0x10000>;
--
2.25.1
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