linux-kernel - [PATCH 6/8] MIPS: c-r4k: Use cache_op function for rm7k

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Date:   Tue, 11 Apr 2023 12:12:23 +0100
From:   Jiaxun Yang <jiaxun.yang@...goat.com>
To:     linux-mips@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, tsbogend@...ha.franken.de,
        and@....com, Jiaxun Yang <jiaxun.yang@...goat.com>
Subject: [PATCH 6/8] MIPS: c-r4k: Use cache_op function for rm7k_erratum31

LLVM assembler is not happy with offset that may overflow immediate field.
Use cache_op function instead of inline assembly to fix build error:

arch/mips/mm/c-r4k.c:922:23: error: instruction requires a CPU feature not
currently enabled
                        "cache\t%1, 0(%0)\n\t"

Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com>
---
 arch/mips/mm/c-r4k.c | 33 ++++++++++++++-------------------
 1 file changed, 14 insertions(+), 19 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 420440cc40b1..89603d033180 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -915,25 +915,20 @@ static inline void rm7k_erratum31(void)
 	write_c0_taghi(0);
 
 	for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
-		__asm__ __volatile__ (
-			".set push\n\t"
-			".set noreorder\n\t"
-			".set "MIPS_ISA_LEVEL"\n\t"
-			"cache\t%1, 0(%0)\n\t"
-			"cache\t%1, 0x1000(%0)\n\t"
-			"cache\t%1, 0x2000(%0)\n\t"
-			"cache\t%1, 0x3000(%0)\n\t"
-			"cache\t%2, 0(%0)\n\t"
-			"cache\t%2, 0x1000(%0)\n\t"
-			"cache\t%2, 0x2000(%0)\n\t"
-			"cache\t%2, 0x3000(%0)\n\t"
-			"cache\t%1, 0(%0)\n\t"
-			"cache\t%1, 0x1000(%0)\n\t"
-			"cache\t%1, 0x2000(%0)\n\t"
-			"cache\t%1, 0x3000(%0)\n\t"
-			".set pop\n"
-			:
-			: "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I));
+		cache_op(Index_Store_Tag_I, addr);
+		cache_op(Index_Store_Tag_I, addr + 0x1000);
+		cache_op(Index_Store_Tag_I, addr + 0x2000);
+		cache_op(Index_Store_Tag_I, addr + 0x3000);
+
+		cache_op(Fill_I, addr);
+		cache_op(Fill_I, addr + 0x1000);
+		cache_op(Fill_I, addr + 0x2000);
+		cache_op(Fill_I, addr + 0x3000);
+
+		cache_op(Index_Store_Tag_I, addr);
+		cache_op(Index_Store_Tag_I, addr + 0x1000);
+		cache_op(Index_Store_Tag_I, addr + 0x2000);
+		cache_op(Index_Store_Tag_I, addr + 0x3000);
 	}
 }
 
-- 
2.39.2 (Apple Git-143)