[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ZDVO/fpOZm+lGVZE@smile.fi.intel.com>
Date: Tue, 11 Apr 2023 15:13:49 +0300
From: Andy Shevchenko <andriy.shevchenko@...el.com>
To: Joy Chakraborty <joychakr@...gle.com>
Cc: Serge Semin <fancer.lancer@...il.com>,
Mark Brown <broonie@...nel.org>, linux-spi@...r.kernel.org,
linux-kernel@...r.kernel.org, manugautam@...gle.com,
rohitner@...gle.com
Subject: Re: [PATCH v5 1/2] spi: dw: Add 32 bpw support to DW DMA Controller
On Thu, Mar 30, 2023 at 06:34:49AM +0000, Joy Chakraborty wrote:
First of all the Subject is wrong. You are not touching DMA controller.
Needs to be rephrased.
> Add Support for AxSize = 4 bytes configuration from dw dma driver if
SPI DMA driver
(or something like this, note capital letters for acronyms).
> n_bytes i.e. number of bytes per write to fifo is 3 or 4.
>
> Number of bytes written to fifo per write is depended on the bits/word
> configuration being used which the DW core driver translates to n_bytes.
...
> static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
> {
> - if (n_bytes == 1)
> + switch (n_bytes) {
> + case 1:
> return DMA_SLAVE_BUSWIDTH_1_BYTE;
> - else if (n_bytes == 2)
> + case 2:
> return DMA_SLAVE_BUSWIDTH_2_BYTES;
> -
> - return DMA_SLAVE_BUSWIDTH_UNDEFINED;
> + case 3:
I'm not sure about this.
> + case 4:
> + return DMA_SLAVE_BUSWIDTH_4_BYTES;
> + default:
> + return DMA_SLAVE_BUSWIDTH_UNDEFINED;
> + }
> }
--
With Best Regards,
Andy Shevchenko
Powered by blists - more mailing lists