lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 12 Apr 2023 10:56:50 +0100
From:   Jonathan Cameron <Jonathan.Cameron@...wei.com>
To:     Greg KH <gregkh@...uxfoundation.org>
CC:     Peter Zijlstra <peterz@...radead.org>,
        Yicong Yang <yangyicong@...wei.com>,
        Mark Rutland <mark.rutland@....com>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Will Deacon <will@...nel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <yangyicong@...ilicon.com>,
        <linuxarm@...wei.com>, Dan Williams <dan.j.williams@...el.com>,
        Shaokun Zhang <zhangshaokun@...ilicon.com>,
        Jiucheng Xu <jiucheng.xu@...ogic.com>,
        "Khuong Dinh" <khuong@...amperecomputing.com>,
        Robert Richter <rric@...nel.org>,
        Atish Patra <atishp@...shpatra.org>,
        Anup Patel <anup@...infault.org>,
        "Andy Gross" <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Frank Li <Frank.li@....com>,
        Shuai Xue <xueshuai@...ux.alibaba.com>,
        Vineet Gupta <vgupta@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Fenghua Yu <fenghua.yu@...el.com>,
        Dave Jiang <dave.jiang@...el.com>, Wu Hao <hao.wu@...el.com>,
        Tom Rix <trix@...hat.com>, <linux-fpga@...r.kernel.org>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Liang Kan <kan.liang@...ux.intel.com>
Subject: Re: [PATCH 01/32] perf: Allow a PMU to have a parent

On Thu, 6 Apr 2023 19:08:45 +0200
Greg KH <gregkh@...uxfoundation.org> wrote:

> On Thu, Apr 06, 2023 at 05:44:45PM +0100, Jonathan Cameron wrote:
> > On Thu, 6 Apr 2023 14:40:40 +0200
> > Peter Zijlstra <peterz@...radead.org> wrote:
> >   
> > > On Thu, Apr 06, 2023 at 11:16:07AM +0100, Jonathan Cameron wrote:
> > >   
> > > > In the long run I agree it would be good.  Short term there are more instances of
> > > > struct pmu that don't have parents than those that do (even after this series).
> > > > We need to figure out what to do about those before adding checks on it being
> > > > set.    
> > > 
> > > Right, I don't think you've touched *any* of the x86 PMUs for example,
> > > and getting everybody that boots an x86 kernel a warning isn't going to
> > > go over well :-)
> > >   
> > 
> > It was tempting :) "Warning: Parentless PMU: try a different architecture."
> > 
> > I'd love some inputs on what the x86 PMU devices parents should be?
> > CPU counters in general tend to just spin out of deep in the architecture code.
> > 
> > My overall favorite is an l2 cache related PMU that is spun up in
> > arch/arm/kernel/irq.c init_IRQ()
> > 
> > I'm just not going to try and figure out why...  
> 
> Why not change the api to force a parent to be passed in?  And if one
> isn't, we make it a "virtual" device and throw it in the class for them?

Longer term I'd be fine doing that, but I'd like to identify the right parents
rather than end up sweeping it under the carpet.  Anything we either get completely
stuck on (or decide we don't care about) could indeed fall back to a virtual
device.

Jonathan


> 
> thanks,
> 
> greg k-h

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ