linux-kernel - [PATCH 17/27] arm64: dts: mediatek: mt6795: Add MMSYS node for multimedia clocks

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Message-Id: <20230412112739.160376-18-angelogioacchino.delregno@collabora.com>
Date:   Wed, 12 Apr 2023 13:27:29 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     matthias.bgg@...il.com
Cc:     p.zabel@...gutronix.de, airlied@...il.com, daniel@...ll.ch,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        jassisinghbrar@...il.com, chunfeng.yun@...iatek.com,
        vkoul@...nel.org, kishon@...nel.org, thierry.reding@...il.com,
        u.kleine-koenig@...gutronix.de, chunkuang.hu@...nel.org,
        angelogioacchino.delregno@...labora.com, ck.hu@...iatek.com,
        jitao.shi@...iatek.com, xinlei.lee@...iatek.com,
        houlong.wei@...iatek.com, dri-devel@...ts.freedesktop.org,
        linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-phy@...ts.infradead.org, linux-pwm@...r.kernel.org,
        kernel@...labora.com, phone-devel@...r.kernel.org,
        ~postmarketos/upstreaming@...ts.sr.ht
Subject: [PATCH 17/27] arm64: dts: mediatek: mt6795: Add MMSYS node for multimedia clocks

Add the MultiMedia System node, providing clocks for the multimedia
hardware blocks and their IOMMU/SMIs.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 99cc4918e6ba..a8b2c4517e79 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -635,6 +635,19 @@ mmc3: mmc@...60000 {
 			status = "disabled";
 		};
 
+		mmsys: syscon@...00000 {
+			compatible = "mediatek,mt6795-mmsys", "syscon";
+			reg = <0 0x14000000 0 0x1000>;
+			power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
+			assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
+			assigned-clock-rates = <400000000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
+		};
+
 		vdecsys: clock-controller@...00000 {
 			compatible = "mediatek,mt6795-vdecsys";
 			reg = <0 0x16000000 0 0x1000>;
-- 
2.40.0