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Message-ID: <ZDgpkK/Dv3y1LUe2@smile.fi.intel.com>
Date:   Thu, 13 Apr 2023 19:10:56 +0300
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Ryan Chen <ryan_chen@...eedtech.com>
Cc:     Brendan Higgins <brendan.higgins@...ux.dev>,
        Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Joel Stanley <joel@....id.au>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Andrew Jeffery <andrew@...id.au>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Wolfram Sang <wsa@...nel.org>, linux-i2c@...r.kernel.org,
        Florian Fainelli <f.fainelli@...il.com>,
        Jean Delvare <jdelvare@...e.de>,
        William Zhang <william.zhang@...adcom.com>,
        Tyrone Ting <kfting@...oton.com>,
        Tharun Kumar P <tharunkumar.pasumarthi@...rochip.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Phil Edworthy <phil.edworthy@...esas.com>,
        openbmc@...ts.ozlabs.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-aspeed@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v9 2/2 RESEND] i2c: aspeed: support ast2600 i2c new
 register mode driver

On Thu, Apr 13, 2023 at 03:53:27PM +0800, Ryan Chen wrote:
> Add i2c new register mode driver to support AST2600 i2c
> new register mode. AST2600 i2c controller have legacy and
> new register mode. The new register mode have global register
> support 4 base clock for scl clock selection, and new clock
> divider mode. The i2c new register mode have separate register
> set to control i2c master and slave.

There is already i2c-aspeed.c in the kernel. Can you elaborate what's wrong
with the extending existing driver? (It seems to me that so called "legacy"
mode is exactly what is being serviced by that driver.)

-- 
With Best Regards,
Andy Shevchenko


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