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Message-ID: <20230413223051.24455-1-jm@ti.com>
Date: Thu, 13 Apr 2023 17:30:46 -0500
From: Judith Mendez <jm@...com>
To: Chandrasekar Ramakrishnan <rcsekar@...sung.com>
CC: Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>,
Andrew Davis <afd@...com>,
Wolfgang Grandegger <wg@...ndegger.com>,
Marc Kleine-Budde <mkl@...gutronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
<linux-can@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>, <netdev@...r.kernel.org>,
Schuyler Patton <spatton@...com>
Subject: [RFC PATCH 0/5] Enable multiple MCAN on AM62x
On AM62x there is one MCAN in MAIN domain and two in MCU domain.
The MCANs in MCU domain were not enabled since there is no
hardware interrupt routed to A53 GIC interrupt controller.
Therefore A53 Linux cannot be interrupted by MCU MCANs.
This solution instantiates a hrtimer with 1 ms polling interval
for a MCAN when there is no hardware interrupt. This hrtimer
generates a recurring software interrupt which allows to call the
isr. The isr will check if there is pending transaction by reading
a register and proceed normally if there is.
On AM62x this series enables two MCU MCAN which will use the hrtimer
implementation. MCANs with hardware interrupt routed to A53 Linux
will continue to use the hardware interrupt as expected.
Timer polling method was tested on both classic CAN and CAN-FD
at 125 KBPS, 250 KBPS, 1 MBPS and 2.5 MBPS with 4 MBPS bitrate
switching.
Letency and CPU load benchmarks were tested on 3x MCAN on AM62x.
1 MBPS timer polling interval is the better timer polling interval
since it has comparable latency to hardware interrupt with the worse
case being 1ms + CAN frame propagation time and CPU load is not
substantial. Latency can be improved further with less than 1 ms
polling intervals, howerver it is at the cost of CPU usage since CPU
load increases at 0.5 ms and lower polling periods than 1ms.
Note that in terms of power, enabling MCU MCANs with timer-polling
implementation might have negative impact since we will have to wake
up every 1 ms whether there are CAN packets pending in the RX FIFO or
not. This might prevent the CPU from entering into deeper idle states
for extended periods of time.
This patch series depends on 'Enable CAN PHY transceiver driver':
https://lore.kernel.org/lkml/775ec9ce-7668-429c-a977-6c8995968d6e@app.fastmail.com/T/
Judith Mendez (5):
arm64: dts: ti: Add AM62x MCAN MAIN domain transceiver overlay
arm64: defconfig: Enable MCAN driver
dt-binding: can: m_can: Remove required interrupt attributes
arm64: dts: ti: Enable multiple MCAN for AM62x in MCU MCAN overlay
can: m_can: Add hrtimer to generate software interrupt
.../bindings/net/can/bosch,m_can.yaml | 2 -
arch/arm64/boot/dts/ti/Makefile | 2 +
.../boot/dts/ti/k3-am625-sk-mcan-main.dtso | 35 +++++++++
.../boot/dts/ti/k3-am625-sk-mcan-mcu.dtso | 75 +++++++++++++++++++
arch/arm64/configs/defconfig | 2 +
drivers/net/can/m_can/m_can.c | 24 +++++-
drivers/net/can/m_can/m_can.h | 3 +
drivers/net/can/m_can/m_can_platform.c | 9 ++-
8 files changed, 146 insertions(+), 6 deletions(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk-mcan-main.dtso
create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk-mcan-mcu.dtso
--
2.17.1
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