linux-kernel - Re: [PATCH 3/3] drm/mediatek: dsi: Add dsi cmdq

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Message-ID: <ef7019930edfbdea53042437818a401f5f50ecd6.camel@mediatek.com>
Date:   Thu, 13 Apr 2023 07:27:32 +0000
From:   Rex-BC Chen (陳柏辰) 
        <Rex-BC.Chen@...iatek.com>
To:     Shuijing Li (李水静) 
        <Shuijing.Li@...iatek.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
        Jitao Shi (石记涛) <jitao.shi@...iatek.com>,
        "daniel@...ll.ch" <daniel@...ll.ch>,
        "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        Xinlei Lee (李昕磊) 
        <Xinlei.Lee@...iatek.com>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
        "airlied@...ux.ie" <airlied@...ux.ie>
CC:     "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH 3/3] drm/mediatek: dsi: Add dsi cmdq_ctl to send panel
 initial code

Hello Xinlei,

IMO, [2/3] is weird because the driver_data for mt8186 and mt8188 are
the same in [2/3]. So I think [2/3] coulde be squashed into this patch.

BRs,
Bo-Chen

On Thu, 2023-04-13 at 14:09 +0800, xinlei.lee@...iatek.com wrote:
> From: Xinlei Lee <xinlei.lee@...iatek.com>
> 
> For mt8188, add dsi cmdq reg control to send long packets to panel
> initialization.
> 
> Signed-off-by: Xinlei Lee <xinlei.lee@...iatek.com>
> Signed-off-by: Jitao Shi <jitao.shi@...iatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 500a3054282d..cbfe5df4647c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -86,6 +86,7 @@
>  
>  #define DSI_CMDQ_SIZE		0x60
>  #define CMDQ_SIZE			0x3f
> +#define CMDQ_SIZE_SEL			BIT(15)
>  
>  #define DSI_HSTX_CKL_WC		0x64
>  
> @@ -178,6 +179,7 @@ struct mtk_dsi_driver_data {
>  	const u32 reg_cmdq_off;
>  	bool has_shadow_ctl;
>  	bool has_size_ctl;
> +	bool cmdq_long_packet_ctl;
>  };
>  
>  struct mtk_dsi {
> @@ -965,6 +967,11 @@ static u32 mtk_dsi_recv_cnt(u8 type, u8
> *read_data)
>  	return 0;
>  }
>  
> +static void mtk_dsi_cmd_packet_ctl(struct mtk_dsi *dsi)
> +{
> +	mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);
> +}
> +
>  static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct
> mipi_dsi_msg *msg)
>  {
>  	const char *tx_buf = msg->tx_buf;
> @@ -996,6 +1003,8 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi,
> const struct mipi_dsi_msg *msg)
>  
>  	mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
>  	mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
> +	if (dsi->driver_data->cmdq_long_packet_ctl)
> +		mtk_dsi_cmd_packet_ctl(dsi);
>  }
>  
>  static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
> @@ -1200,18 +1209,21 @@ static const struct mtk_dsi_driver_data
> mt8183_dsi_driver_data = {
>  	.reg_cmdq_off = 0x200,
>  	.has_shadow_ctl = true,
>  	.has_size_ctl = true,
> +	.cmdq_long_packet_ctl = false,
>  };
>  
>  static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
>  	.reg_cmdq_off = 0xd00,
>  	.has_shadow_ctl = true,
>  	.has_size_ctl = true,
> +	.cmdq_long_packet_ctl = false,
>  };
>  
>  static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
>  	.reg_cmdq_off = 0xd00,
>  	.has_shadow_ctl = true,
>  	.has_size_ctl = true,
> +	.cmdq_long_packet_ctl = true,
>  };
>  
>  static const struct of_device_id mtk_dsi_of_match[] = {