linux-kernel - Re: [PATCH v8 5/7] cache: Add L2 cache management for Andes AX45MP RISC-V core

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Message-ID: <CA+V-a8vV0rnOo6bLmegu5gAqA3-jfOn6hknG12jAtYXce0haLQ@mail.gmail.com>
Date:   Fri, 14 Apr 2023 19:59:37 +0100
From:   "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To:     Conor Dooley <conor@...nel.org>, Heiko Stuebner <heiko@...ech.de>
Cc:     Conor Dooley <conor.dooley@...rochip.com>,
        Arnd Bergmann <arnd@...db.de>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Guo Ren <guoren@...nel.org>,
        Andrew Jones <ajones@...tanamicro.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Samuel Holland <samuel@...lland.org>,
        linux-riscv@...ts.infradead.org, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org,
        Biju Das <biju.das.jz@...renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v8 5/7] cache: Add L2 cache management for Andes AX45MP
 RISC-V core

On Thu, Apr 13, 2023 at 10:06 PM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
>
> On Thu, Apr 13, 2023 at 7:46 PM Conor Dooley <conor@...nel.org> wrote:
> >
> > > Is
> > > dma-noncoherent.c also valid for RISCV-32? If not then we can make
> > > pmem.c compile conditionally if DMA non-coherenet is enabled and we
> > > make DMA non-coherent depend on 64bit.
> >
> > Could you drop the {s,l}d in exchange for {s,l}w instead, or am I
> > progressing even further into braino territory?
> Just the direct exchange wont work in addition shifting + oring to
> take care of 64-bit will require. (Correct me if I'm wrong here)
>
> I was wondering now if we need to store/restore the s0 and ra
> registers. I stumbled on an X86 implementation which has call [0] in
> the ALTERNATIVE_X() macro but here we dont store/restore the
> registers. Is the RISC-V implementation of ALT macro different
> compared to x86?
>
I did try a call without stroe/restore of s0 and ra registers and that
didn't work!. So I have re-written the assembly code which makes
32-bit RISC-V compilers happy. Once done with the testing I'll send a
new version of this series. Hopefully the last ;)

Cheers,
Prabhakar