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Message-ID: <20230414024157.53203-1-xingyu.wu@starfivetech.com>
Date: Fri, 14 Apr 2023 10:41:50 +0800
From: Xingyu Wu <xingyu.wu@...rfivetech.com>
To: <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
"Michael Turquette" <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Conor Dooley <conor@...nel.org>,
"Emil Renner Berthing" <kernel@...il.dk>
CC: Rob Herring <robh+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
Xingyu Wu <xingyu.wu@...rfivetech.com>,
William Qiu <william.qiu@...rfivetech.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: [PATCH v3 0/7] Add PLL clocks driver for StarFive JH7110 SoC
This patch serises are to add PLL clocks driver and providers by writing
and reading syscon registers for the StarFive JH7110 RISC-V SoC. And add
documentation to describe StarFive System Controller(syscon) Registers.
PLL are high speed, low jitter frequency synthesizers in JH7110.
Each PLL clocks work in integer mode or fraction mode by some dividers,
and the dividers are set in several syscon registers.
The formula for calculating frequency is:
Fvco = Fref * (NI + NF) / M / Q1
The first patch adds docunmentation to describe PLL clock bindings,
and the second patch adds driver to support PLL clocks for JH7110.
The patch 3 modifies the SYSCRG dibindings and adds PLL clock inputs.
The patch 4 modifies the system clock driver and changes PLL clock source
from PLL clock controller instead of the fixed factor clocks. The patch 5
adds documentation to decribe syscon registers. And the patch 6 adds the
stg/sys/aon syscon nodes for JH7110 SoC. The last patch adds PLL
clock node and modifies the syscrg node in JH7110 dts file.
This patchset should be applied after these patchset about JH7110 basic
clock drivers(Accepted and will merged in v6.4)[1].
[1] https://lore.kernel.org/all/20230401111934.130844-1-hal.feng@starfivetech.com/
Changes since v2:
- Rebased on latest JH7110 basic clock drivers.
- Added the complete documentation to describe syscon register.
- Added syscon node in JH7110 dts file.
- Modified the clock rate selection to match the closest rate in
PLL driver when setting rate.
v2: https://lore.kernel.org/all/20230316030514.137427-1-xingyu.wu@starfivetech.com/
Changes since v1:
- Changed PLL clock node to be child of syscon node in dts.
- Modifed the definitions and names of function in PLL clock driver.
- Added commit to update syscon and syscrg dt-bindings.
v1: https://lore.kernel.org/all/20230221141147.303642-1-xingyu.wu@starfivetech.com/
William Qiu (2):
dt-bindings: soc: starfive: Add StarFive syscon module
riscv: dts: starfive: jh7110: Add syscon nodes
Xingyu Wu (5):
dt-bindings: clock: Add StarFive JH7110 PLL clock generator
clk: starfive: Add StarFive JH7110 PLL clock driver
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
clk: starfive: jh7110-sys: Modify PLL clocks source
riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg
node
.../bindings/clock/starfive,jh7110-pll.yaml | 46 ++
.../clock/starfive,jh7110-syscrg.yaml | 20 +-
.../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++
MAINTAINERS | 12 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 29 +-
drivers/clk/starfive/Kconfig | 9 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jh7110-pll.c | 427 ++++++++++++++++++
.../clk/starfive/clk-starfive-jh7110-pll.h | 293 ++++++++++++
.../clk/starfive/clk-starfive-jh7110-sys.c | 31 +-
.../dt-bindings/clock/starfive,jh7110-crg.h | 6 +
11 files changed, 903 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.h
base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
prerequisite-patch-id: 388b8adbb0fe2daf4d07a21eafd4f1bd50ce2403
prerequisite-patch-id: 1117ecaa40a353c667b71802ab34ecf9568d8bb2
prerequisite-patch-id: b00c6b21fbd0353d88b7c9b09093ba30b765f45b
prerequisite-patch-id: 08ec9027e8a5c6fdf201726833168c7464a9b94d
prerequisite-patch-id: fb5120248e48fe1faf053ae0b490c92507ec2b44
prerequisite-patch-id: 4b93d8d590b0a2abe7b4be5287232c494c35be4a
prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d
prerequisite-patch-id: c09c4c68af017b8e5c97b515cb50b70c18a2e705
prerequisite-patch-id: 0df8ccb0e848c2df4c2da95026494bebecede92d
prerequisite-patch-id: 315303931e4b6499de7127a88113763f86e97e16
prerequisite-patch-id: 40cb8212ddb024c20593f73d8b87d9894877e172
prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
prerequisite-patch-id: d57cc467fb036241b9276320ff076c4a30d376d6
prerequisite-patch-id: 6e563d68bc5dbf951d4ced17897f9cc4d56169fe
prerequisite-patch-id: 61ec2caa21fd0fc60e57977f7d16d3f72b135745
prerequisite-patch-id: 1387a7e87b446329dfc21f3e575ceae7ebcf954c
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
prerequisite-patch-id: 9007c8610fdcd387592475949864edde874c20a2
prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
prerequisite-patch-id: 0a0ac5a8a90655b415f6b62e324f3db083cdaaee
--
2.25.1
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