linux-kernel - Re: [PATCH v4 0/4] cacheinfo: Correctly fallback to using clidr

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Message-ID: <15abdf3e-1a01-a568-9089-625e771c9d53@gmail.com>
Date:   Fri, 14 Apr 2023 15:36:08 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Pierre Gondois <pierre.gondois@....com>,
        linux-kernel@...r.kernel.org
Cc:     Radu Rendec <rrendec@...hat.com>,
        Alexandre Ghiti <alexghiti@...osinc.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Will Deacon <will@...nel.org>,
        Sudeep Holla <sudeep.holla@....com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Palmer Dabbelt <palmer@...osinc.com>,
        Gavin Shan <gshan@...hat.com>
Subject: Re: [PATCH v4 0/4] cacheinfo: Correctly fallback to using clidr_el1's
 information

On 4/14/23 01:14, Pierre Gondois wrote:
> v4:
> arch_topology: Remove early cacheinfo error message:
> - Only remove the error message if the error code is -ENOENT
> cacheinfo: Add use_arch[|_cache]_info field/function:
> - Use a static variable instead of a per-leaf 'use_arch_info'
> - Reformat the use_arch_cache_info() define
> 
> v3:
> cacheinfo: Check sib_leaf in cache_leaves_are_shared():
> - Reformulate commit message
> - Fix rebase issue and move '&&' condition which was in the last patch
>    to this patch.
> cacheinfo: Add use_arch[|_cache]_info field/function:
> - Put the function declaration in one line.
> arch_topology: Remove early cacheinfo error message:
> - New patch.
> 
> v2:
> cacheinfo: Check sib_leaf in cache_leaves_are_shared()
> - Reformulate commit message
> - Add 'Fixes: f16d1becf96f ("cacheinfo: Use cache identifiers [...]'
> cacheinfo: Check cache properties are present in DT
> - Use of_property_present()
> - Add 'Reported-by: Alexandre Ghiti <alexghiti@...osinc.com>'
> cacheinfo: Add use_arch[|_cache]_info field/function:
> - Make use_arch_cache_info() a static inline function
> 
> The cache information can be extracted from either a Device
> Tree (DT), the PPTT ACPI table, or arch registers (clidr_el1
> for arm64).
> 
> When the DT is used but no cache properties are advertised,
> the current code doesn't correctly fallback to using arch information.
> 
> Correct this. Also use the assumption that L1 data/instruction caches
> are private and L2/higher caches are shared when the cache information
> is coming form clidr_el1.
> 
> As suggested by Alexandre, this serie should ideally go to 6.3 fixes.

FWIW:

Tested-by: Florian Fainelli <f.fainelli@...il.com>

Thanks!
-- 
Florian