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Message-ID: <BY5PR12MB425810A4B57D1C12AE170927DB999@BY5PR12MB4258.namprd12.prod.outlook.com>
Date: Fri, 14 Apr 2023 06:05:15 +0000
From: "Potthuri, Sai Krishna" <sai.krishna.potthuri@....com>
To: Mark Brown <broonie@...nel.org>
CC: "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"git (AMD-Xilinx)" <git@....com>,
"saikrishna12468@...il.com" <saikrishna12468@...il.com>
Subject: RE: [PATCH 0/2] spi: cadence-quadspi: Fix random issues with Xilinx
Versal DMA read
> -----Original Message-----
> From: Sai Krishna Potthuri <sai.krishna.potthuri@....com>
> Sent: Monday, March 20, 2023 3:29 PM
> To: Mark Brown <broonie@...nel.org>
> Cc: linux-spi@...r.kernel.org; linux-kernel@...r.kernel.org; git (AMD-Xilinx)
> <git@....com>; saikrishna12468@...il.com; Potthuri, Sai Krishna
> <sai.krishna.potthuri@....com>
> Subject: [PATCH 0/2] spi: cadence-quadspi: Fix random issues with Xilinx Versal
> DMA read
>
> Update Xilinx Versal external DMA read logic to fix random issues
> - Instead of having the fixed timeout, update the read timeout based on the
> length of the transfer to avoid timeout for larger data size.
> - While switching between external DMA read and indirect read, disable the SPI
> before configuration and enable it after configuration as recommended by Octal-
> SPI Flash Controller specification.
>
> Sai Krishna Potthuri (2):
> spi: cadence-quadspi: Update the read timeout based on the length
> spi: cadence-quadspi: Disable the SPI before reconfiguring
>
> drivers/spi/spi-cadence-quadspi.c | 40 ++++++++++++++++++-------------
> 1 file changed, 24 insertions(+), 16 deletions(-)
>
> --
Mark: Do you have any comments on this series?
Regards
Sai Krishna
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