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Date: Fri, 14 Apr 2023 16:28:31 +0530
From: Devi Priya <quic_devipriy@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@...aro.org>, <agross@...nel.org>,
<andersson@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <linus.walleij@...aro.org>,
<catalin.marinas@....com>, <will@...nel.org>,
<p.zabel@...gutronix.de>, <shawnguo@...nel.org>, <arnd@...db.de>,
<marcel.ziswiler@...adex.com>, <dmitry.baryshkov@...aro.org>,
<geert+renesas@...der.be>, <rafal@...ecki.pl>,
<nfraprado@...labora.com>, <broonie@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<linux-gpio@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
CC: <quic_srichara@...cinc.com>, <quic_gokulsri@...cinc.com>,
<quic_sjaganat@...cinc.com>, <quic_kathirav@...cinc.com>,
<quic_arajkuma@...cinc.com>, <quic_anusha@...cinc.com>,
<quic_poovendh@...cinc.com>
Subject: Re: [PATCH V12 3/4] arm64: dts: qcom: Add support for ipq9574 SoC and
RDP433 variant
On 4/14/2023 4:27 PM, Konrad Dybcio wrote:
>
>
> On 14.04.2023 12:01, Devi Priya wrote:
>>
>>
>> On 4/13/2023 2:16 AM, Konrad Dybcio wrote:
>>>
>>>
>>> On 10.04.2023 15:59, Devi Priya wrote:
>>>> Add initial device tree support for Qualcomm IPQ9574 SoC and
>>>> Reference Design Platform(RDP) 433 which is based on IPQ9574
>>>> family of SoCs
>>>>
>>>> Co-developed-by: Anusha Rao <quic_anusha@...cinc.com>
>>>> Signed-off-by: Anusha Rao <quic_anusha@...cinc.com>
>>>> Co-developed-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
>>>> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@...cinc.com>
>>>> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
>>>> ---
>>>
>>>> + soc: soc@0 {
>>>> + compatible = "simple-bus";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges = <0 0 0 0xffffffff>;
>>> this is equal to:
>>>
>>> ranges;
>>
>> Konrad, on updating (ranges = <0 0 0 0xffffffff>; --> ranges;)
>> we see the below warnings:
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi:103.3-10: Warning (ranges_format):
>> /soc@0:ranges: empty "ranges" property but its #address-cells (1)
>> differs from / (2)
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi:103.3-10: Warning (ranges_format): /soc@0:ranges: empty "ranges" property but its #size-cells (1) differs
>> from / (2)
>>
>> Looks like, empty ranges property isn't supported if the parent and
>> child address spaces are non-identical.
>> Would you suggest to retain the ranges as such?
>> (ranges = <0 0 0 0xffffffff>;)
>>
>> Thanks,
>> Devi Priya
> Oh right, you have address/size cells = 2 at the top level.
> Forget about this change.
Yup, thanks!
Best Regards,
Devi Priya
>
> Konrad
>>>
>>> Could you fix that up when applying, Bjorn, should there be
>>> no other issues?
>>>
>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
>>>
>> Thank you!
>>> Konrad
>>>
>>>> +
>>>> + tlmm: pinctrl@...0000 {
>>>> + compatible = "qcom,ipq9574-tlmm";
>>>> + reg = <0x01000000 0x300000>;
>>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>> + gpio-controller;
>>>> + #gpio-cells = <2>;
>>>> + gpio-ranges = <&tlmm 0 0 65>;
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <2>;
>>>> +
>>>> + uart2_pins: uart2-state {
>>>> + pins = "gpio34", "gpio35";
>>>> + function = "blsp2_uart";
>>>> + drive-strength = <8>;
>>>> + bias-disable;
>>>> + };
>>>> + };
>>>> +
>>>> + gcc: clock-controller@...0000 {
>>>> + compatible = "qcom,ipq9574-gcc";
>>>> + reg = <0x01800000 0x80000>;
>>>> + clocks = <&xo_board_clk>,
>>>> + <&sleep_clk>,
>>>> + <0>,
>>>> + <0>,
>>>> + <0>,
>>>> + <0>,
>>>> + <0>;
>>>> + #clock-cells = <1>;
>>>> + #reset-cells = <1>;
>>>> + #power-domain-cells = <1>;
>>>> + };
>>>> +
>>>> + sdhc_1: mmc@...4000 {
>>>> + compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
>>>> + reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
>>>> + reg-names = "hc", "cqhci";
>>>> +
>>>> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>>>> + interrupt-names = "hc_irq", "pwr_irq";
>>>> +
>>>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>>>> + <&gcc GCC_SDCC1_APPS_CLK>,
>>>> + <&xo_board_clk>;
>>>> + clock-names = "iface", "core", "xo";
>>>> + non-removable;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + blsp1_uart2: serial@...1000 {
>>>> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>>>> + reg = <0x078b1000 0x200>;
>>>> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>>>> + <&gcc GCC_BLSP1_AHB_CLK>;
>>>> + clock-names = "core", "iface";
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + intc: interrupt-controller@...0000 {
>>>> + compatible = "qcom,msm-qgic2";
>>>> + reg = <0x0b000000 0x1000>, /* GICD */
>>>> + <0x0b002000 0x2000>, /* GICC */
>>>> + <0x0b001000 0x1000>, /* GICH */
>>>> + <0x0b004000 0x2000>; /* GICV */
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <3>;
>>>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>>> + ranges = <0 0x0b00c000 0x3000>;
>>>> +
>>>> + v2m0: v2m@0 {
>>>> + compatible = "arm,gic-v2m-frame";
>>>> + reg = <0x00000000 0xffd>;
>>>> + msi-controller;
>>>> + };
>>>> +
>>>> + v2m1: v2m@...0 {
>>>> + compatible = "arm,gic-v2m-frame";
>>>> + reg = <0x00001000 0xffd>;
>>>> + msi-controller;
>>>> + };
>>>> +
>>>> + v2m2: v2m@...0 {
>>>> + compatible = "arm,gic-v2m-frame";
>>>> + reg = <0x00002000 0xffd>;
>>>> + msi-controller;
>>>> + };
>>>> + };
>>>> +
>>>> + timer@...0000 {
>>>> + compatible = "arm,armv7-timer-mem";
>>>> + reg = <0x0b120000 0x1000>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges;
>>>> +
>>>> + frame@...0000 {
>>>> + reg = <0x0b121000 0x1000>,
>>>> + <0x0b122000 0x1000>;
>>>> + frame-number = <0>;
>>>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>>>> + };
>>>> +
>>>> + frame@...3000 {
>>>> + reg = <0x0b123000 0x1000>;
>>>> + frame-number = <1>;
>>>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + frame@...4000 {
>>>> + reg = <0x0b124000 0x1000>;
>>>> + frame-number = <2>;
>>>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + frame@...5000 {
>>>> + reg = <0x0b125000 0x1000>;
>>>> + frame-number = <3>;
>>>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + frame@...6000 {
>>>> + reg = <0x0b126000 0x1000>;
>>>> + frame-number = <4>;
>>>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + frame@...7000 {
>>>> + reg = <0x0b127000 0x1000>;
>>>> + frame-number = <5>;
>>>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + frame@...8000 {
>>>> + reg = <0x0b128000 0x1000>;
>>>> + frame-number = <6>;
>>>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>>>> + status = "disabled";
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + timer {
>>>> + compatible = "arm,armv8-timer";
>>>> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>>>> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>>>> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>>>> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>>>> + };
>>>> +};
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