linux-kernel - Re: [PATCH] x86/cpufeatures: extend CPUID leaf 0xc0000001 support for Zhaoxin

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Message-ID: <7866e99a-df88-14fa-92ae-c5b5d176724b@zhaoxin.com>
Date:   Fri, 14 Apr 2023 21:14:17 +0800
From:   Tony W Wang-oc <TonyWWang-oc@...oxin.com>
To:     Borislav Petkov <bp@...en8.de>
CC:     <tglx@...utronix.de>, <mingo@...hat.com>,
        <dave.hansen@...ux.intel.com>, <hpa@...or.com>, <x86@...nel.org>,
        <linux-kernel@...r.kernel.org>, <peterz@...radead.org>,
        <seanjc@...gle.com>, <pbonzini@...hat.com>, <kim.phillips@....com>,
        <babu.moger@....com>, <pawan.kumar.gupta@...ux.intel.com>,
        <sandipan.das@....com>, <CobeChen@...oxin.com>,
        <TimGuo@...oxin.com>, <LeoLiu-oc@...oxin.com>
Subject: Re: [PATCH] x86/cpufeatures: extend CPUID leaf 0xc0000001 support for
 Zhaoxin



On 4/14/23 18:48, Borislav Petkov wrote:
> On Fri, Apr 14, 2023 at 05:53:34PM +0800, Tony W Wang-oc wrote:
>> Extend CPUID leaf 0xc0000001 to support SM2, SM3, SM4, PARALLAX, TM3,
>> RNG2, PHE2, RSA.
>>
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 0]  SM2
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 1]  SM2_EN
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 4]  SM3 SM4
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 5]  SM3_EN SM4_EN
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 16] PARALLAX
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 17] PARALLAX_EN
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 20] TM3
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 21] TM3_EN
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 22] RNG2
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 23] RNG2_EN
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 25] PHE2
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 26] PHE2_EN
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 27] RSA
>> CPUID.(EAX=0xc0000001,ECX=0):EDX[bit 28] RSA_EN
> 
> None of those flags are used in code, why do we need this patch?
> 
 The instructions about these flags can be executed at any privilege
level. I think using these flags in kernel mode is a case. This patch
shows the statement of these flags to the user mode explicitly. So users
can see and use these CPU features conveniently.

> If you want to dump them on the hardware to know what's set or not,
> there's tools/arch/x86/kcpuid/ for that.
> 
>> SM2/SM3/SM4 imply the instructions support for Chinese cipher security
>> algorithm generations 2/3/4.
>> PARALLAX is the feature of Zhaoxin CPU that automatically adjusts
>> processors's voltage as a function of temperature.
>> TM3 is the abbreviation of Thermal Monitor version 3.
>> RNG2 is the abbreviation of Random Number Generation version 2.
>> PHE2 is the abbreviation of Padlock Hash Engine version 2.
>> RSA implies Zhaoxin hardware support for RSA algorithm.
>>
>> All these features have two relative CPUID bits, one bit implies the
>> existence of the feature and the other bit with postfix "EN" implies
>> the availability of this feature.
> 
> That's a lot of waste of CPUID bits but that's your decision.
> 
Sorry about that.
This implementation aimed to control or statement these features
independently.

Sincerely
TonyWWangoc