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Date:   Fri, 14 Apr 2023 08:48:43 -0700
From:   Abhinav Kumar <quic_abhinavk@...cinc.com>
To:     Marijn Suijten <marijn.suijten@...ainline.org>
CC:     Kuogee Hsieh <quic_khsieh@...cinc.com>, <robdclark@...il.com>,
        <sean@...rly.run>, <swboyd@...omium.org>, <dianders@...omium.org>,
        <vkoul@...nel.org>, <daniel@...ll.ch>, <airlied@...il.com>,
        <agross@...nel.org>, <dmitry.baryshkov@...aro.org>,
        <andersson@...nel.org>, <quic_sbillaka@...cinc.com>,
        <freedreno@...ts.freedesktop.org>,
        <dri-devel@...ts.freedesktop.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/msm/dpu: always program dsc active bits



On 4/14/2023 12:35 AM, Marijn Suijten wrote:
> On 2023-04-12 10:33:15, Abhinav Kumar wrote:
> [..]
>>> What happens if a device boots without DSC panel connected?  Will
>>> CTL_DSC_FLUSH be zero and not (unnecessarily, I assume) flush any of the
>>> DSC blocks?  Or could this flush uninitialized state to the block?
>>>
>>
>> If we bootup without DSC panel connected, the kernel's cfg->dsc will be
>> 0 and default register value of CTL_DSC_FLUSH will be 0 so it wont flush
>> any DSC blocks.
> 
> Ack, that makes sense.  However, if I connect a DSC panel, then
> disconnect it (now the register should be non-zero, but cfg->dsc will be
> zero), and then replug a non-DSC panel multiple times, it'll get flushed
> every time because we never clear CTL_DSC_FLUSH after that?
> 

If we remove it after kernel starts, that issue is there even today 
without that change because DSI is not a hot-pluggable display so a 
teardown wont happen when you plug out the panel. How will cfg->dsc be 0 
then? In that case, its not a valid test as there was no indication to 
DRM that display was disconnected so we cannot tear it down.

>> Sure, as I wrote in the other response, we can move this
>> to reset_intf_cfg later when the other pieces are fixed. And leave a
>> FIXME here.
> 
> Kuogee forgot to CC me on this patchs so I did not read/receive that
> side of the email thread.  Will catch up before reviewing v2.
> 
> - Marijn

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