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Message-Id: <20230415-mmc-hi3798mv200-v2-2-1d274f9b71da@outlook.com>
Date: Sun, 16 Apr 2023 01:13:17 +0800
From: Yang Xiwen via B4 Relay
<devnull+forbidden405.outlook.com@...nel.org>
To: Ulf Hansson <ulf.hansson@...aro.org>,
Jaehoon Chung <jh80.chung@...sung.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Yang Xiwen <forbidden405@...look.com>
Cc: tianshuliang <tianshuliang@...ilicon.com>,
Jiancheng Xue <xuejiancheng@...ilicon.com>,
Shawn Guo <shawn.guo@...aro.org>,
David Yang <mmyangfl@...il.com>, linux-mmc@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: [PATCH RFC v2 2/3] mmc: dw_mmc-histb: add support for hi3798mv200
From: Yang Xiwen <forbidden405@...look.com>
Add support for Hi3798MV200 specific extension.
Signed-off-by: Yang Xiwen <forbidden405@...look.com>
---
drivers/mmc/host/dw_mmc-histb.c | 110 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 109 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/dw_mmc-histb.c b/drivers/mmc/host/dw_mmc-histb.c
index 106e586bcff4b..039b6df0e8c4d 100644
--- a/drivers/mmc/host/dw_mmc-histb.c
+++ b/drivers/mmc/host/dw_mmc-histb.c
@@ -16,10 +16,14 @@
#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
+#define SDMMC_TUNING_CTRL 0x118
+#define SDMMC_TUNING_FIND_EDGE BIT(5)
+
#define ALL_INT_CLR 0x1ffff
enum dw_mci_histb_type {
DW_MCI_TYPE_HI3798CV200,
+ DW_MCI_TYPE_HI3798MV200,
};
static struct dw_mci_histb_compat {
@@ -29,6 +33,9 @@ static struct dw_mci_histb_compat {
{
.compatible = "hisilicon,hi3798cv200-dw-mshc",
.ctrl_type = DW_MCI_TYPE_HI3798CV200,
+ }, {
+ .compatible = "hisilicon,hi3798mv200-dw-mshc",
+ .ctrl_type = DW_MCI_TYPE_HI3798MV200,
},
};
@@ -36,6 +43,7 @@ struct dw_mci_histb_priv {
enum dw_mci_histb_type ctrl_type;
struct clk *sample_clk;
struct clk *drive_clk;
+ struct clk *sap_dll_mode_clk;
};
static void dw_mci_histb_set_ios(struct dw_mci *host, struct mmc_ios *ios)
@@ -68,7 +76,10 @@ static void dw_mci_histb_set_ios(struct dw_mci *host, struct mmc_ios *ios)
if (ios->timing == MMC_TIMING_MMC_HS ||
ios->timing == MMC_TIMING_LEGACY)
clk_set_phase(priv->drive_clk, 180);
- else if (ios->timing == MMC_TIMING_MMC_HS200)
+ else if (ios->timing == MMC_TIMING_MMC_DDR52) {
+ clk_set_phase(priv->drive_clk, 90);
+ clk_set_phase(priv->sample_clk, 45);
+ } else if (ios->timing == MMC_TIMING_MMC_HS200)
clk_set_phase(priv->drive_clk, 135);
}
@@ -133,6 +144,75 @@ static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot,
return err;
}
+static int dw_mci_hi3798mv200_execute_tuning_mix_mode(struct dw_mci_slot *slot,
+ u32 opcode)
+{
+ static const int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 };
+ struct dw_mci *host = slot->host;
+ struct dw_mci_histb_priv *priv = host->priv;
+ int raise_point = -1, fall_point = -1;
+ int err, prev_err = -1;
+ int found = 0;
+ int regval;
+ int i;
+
+ clk_disable(priv->sap_dll_mode_clk);
+ for (i = 0; i < ARRAY_SIZE(degrees); i++) {
+ clk_set_phase(priv->sample_clk, degrees[i]);
+ mci_writel(host, RINTSTS, ALL_INT_CLR);
+
+ err = mmc_send_tuning(slot->mmc, opcode, NULL);
+ if (err)
+ found = 1;
+ else {
+ regval = mci_readl(host, TUNING_CTRL);
+ if (regval & SDMMC_TUNING_FIND_EDGE)
+ found = 1;
+ };
+
+ if (i > 0) {
+ if (err && !prev_err)
+ fall_point = i - 1;
+ if (!err && prev_err)
+ raise_point = i;
+ }
+
+ if (raise_point != -1 && fall_point != -1)
+ goto tuning_out;
+
+ prev_err = err;
+ err = 0;
+ }
+
+tuning_out:
+ clk_enable(priv->sap_dll_mode_clk);
+ if (found) {
+ if (raise_point == -1)
+ raise_point = 0;
+ if (fall_point == -1)
+ fall_point = ARRAY_SIZE(degrees) - 1;
+ if (fall_point < raise_point) {
+ if ((raise_point + fall_point) >
+ (ARRAY_SIZE(degrees) - 1))
+ i = fall_point / 2;
+ else
+ i = (raise_point + ARRAY_SIZE(degrees) - 1) / 2;
+ } else {
+ i = (raise_point + fall_point) / 2;
+ }
+
+ clk_set_phase(priv->sample_clk, degrees[i]);
+ dev_dbg(host->dev, "Tuning clk_sample[%d, %d], set[%d]\n",
+ raise_point, fall_point, degrees[i]);
+ } else {
+ dev_err(host->dev, "No valid clk_sample shift! use default\n");
+ err = -EINVAL;
+ }
+
+ mci_writel(host, RINTSTS, ALL_INT_CLR);
+ return err;
+}
+
static int dw_mci_histb_init(struct dw_mci *host)
{
struct dw_mci_histb_priv *priv;
@@ -160,6 +240,14 @@ static int dw_mci_histb_init(struct dw_mci *host)
return PTR_ERR(priv->drive_clk);
}
+ if (priv->ctrl_type == DW_MCI_TYPE_HI3798MV200) {
+ priv->sap_dll_mode_clk = devm_clk_get(host->dev, "sap-dll-mode");
+ if (IS_ERR(priv->sap_dll_mode_clk)) {
+ dev_err(host->dev, "failed to get sap-dll-mode clock\n");
+ return PTR_ERR(priv->sap_dll_mode_clk);
+ }
+ }
+
ret = clk_prepare_enable(priv->sample_clk);
if (ret) {
dev_err(host->dev, "failed to enable ciu-sample clock\n");
@@ -172,9 +260,19 @@ static int dw_mci_histb_init(struct dw_mci *host)
goto disable_sample_clk;
}
+ if (priv->ctrl_type == DW_MCI_TYPE_HI3798MV200) {
+ ret = clk_prepare_enable(priv->sap_dll_mode_clk);
+ if (ret) {
+ dev_err(host->dev, "failed to disable tuning mode");
+ goto disable_drive_clk;
+ }
+ }
+
host->priv = priv;
return 0;
+disable_drive_clk:
+ clk_disable_unprepare(priv->drive_clk);
disable_sample_clk:
clk_disable_unprepare(priv->sample_clk);
return ret;
@@ -187,8 +285,16 @@ static const struct dw_mci_drv_data hi3798cv200_data = {
.execute_tuning = dw_mci_hi3798cv200_execute_tuning,
};
+static const struct dw_mci_drv_data hi3798mv200_data = {
+ .common_caps = MMC_CAP_CMD23,
+ .init = dw_mci_histb_init,
+ .set_ios = dw_mci_histb_set_ios,
+ .execute_tuning = dw_mci_hi3798mv200_execute_tuning_mix_mode,
+};
+
static const struct of_device_id dw_mci_histb_match[] = {
{ .compatible = "hisilicon,hi3798cv200-dw-mshc", .data = &hi3798cv200_data },
+ { .compatible = "hisilicon,hi3798mv200-dw-mshc", .data = &hi3798mv200_data },
{},
};
@@ -208,6 +314,8 @@ static int dw_mci_histb_remove(struct platform_device *pdev)
clk_disable_unprepare(priv->drive_clk);
clk_disable_unprepare(priv->sample_clk);
+ if (priv->ctrl_type == DW_MCI_TYPE_HI3798MV200)
+ clk_disable_unprepare(priv->sap_dll_mode_clk);
dw_mci_pltfm_remove(pdev);
--
2.39.2
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