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Message-ID: <20230416-failing-washbasin-e4fa5caea267-mkl@pengutronix.de>
Date: Sun, 16 Apr 2023 17:35:33 +0200
From: Marc Kleine-Budde <mkl@...gutronix.de>
To: Oliver Hartkopp <socketcan@...tkopp.net>
Cc: Judith Mendez <jm@...com>,
Chandrasekar Ramakrishnan <rcsekar@...sung.com>,
Nishanth Menon <nm@...com>,
Vignesh Raghavendra <vigneshr@...com>,
Andrew Davis <afd@...com>,
Wolfgang Grandegger <wg@...ndegger.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-can@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, netdev@...r.kernel.org,
Schuyler Patton <spatton@...com>
Subject: Re: [RFC PATCH 5/5] can: m_can: Add hrtimer to generate software
interrupt
On 16.04.2023 14:33:11, Oliver Hartkopp wrote:
>
>
> On 4/14/23 20:20, Marc Kleine-Budde wrote:
> > On 13.04.2023 17:30:51, Judith Mendez wrote:
> > > Add a hrtimer to MCAN struct. Each MCAN will have its own
> > > hrtimer instantiated if there is no hardware interrupt found.
> > >
> > > The hrtimer will generate a software interrupt every 1 ms. In
> >
> > Are you sure about the 1ms?
I had the 5ms that are actually used in the code in mind. But this is a
good calculation.
> The "shortest" 11 bit CAN ID CAN frame is a Classical CAN frame with DLC = 0
> and 1 Mbit/s (arbitration) bitrate. This should be 48 bits @1Mbit => ~50
> usecs
>
> So it should be something about
>
> 50 usecs * (FIFO queue len - 2)
Where does the "2" come from?
> if there is some FIFO involved, right?
Yes, the mcan core has a FIFO. In the current driver the FIFO
configuration is done via device tree and fixed after that. And I don't
know the size of the available RAM in the mcan IP core on that TI SoC.
Marc
--
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