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Message-ID: <CAFBinCCEhobbyKHuKDWzTYCQWgNT1-e8=7hMhq1mvT6CuEOjGw@mail.gmail.com>
Date: Sun, 16 Apr 2023 22:54:17 +0200
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: Dmitry Rokosov <ddrokosov@...rdevices.ru>
Cc: gregkh@...uxfoundation.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, neil.armstrong@...aro.org,
khilman@...libre.com, jbrunet@...libre.com,
mturquette@...libre.com, vkoul@...nel.org, kishon@...nel.org,
hminas@...opsys.com, Thinh.Nguyen@...opsys.com,
yue.wang@...ogic.com, hanjie.lin@...ogic.com,
kernel@...rdevices.ru, rockosov@...il.com,
linux-usb@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, linux-phy@...ts.infradead.org
Subject: Re: [PATCH v1 1/5] phy: amlogic: during USB PHY clkin obtaining,
enable it
Hi Dmitry,
On Fri, Apr 14, 2023 at 5:24 PM Dmitry Rokosov <ddrokosov@...rdevices.ru> wrote:
[...]
> - priv->clk = devm_clk_get(dev, "xtal");
> + priv->clk = devm_clk_get_enabled(dev, "xtal");
Generally this works fine but I wouldn't recommend this approach if:
- there's some required wait time after the clock has been enabled
(see phy_meson_g12a_usb2_init - there's already some required wait
time after triggering the reset)
- clock gating (for power saving) is needed when the dwc3 driver is
unloaded by the PHY driver is not
In this case: just manually manage the clock in phy_meson_g12a_usb2_{init,exit}
Best regards,
Martin
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