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Message-ID: <5a3a800a-da9b-1155-f7e7-f315887baf00@linaro.org>
Date: Mon, 17 Apr 2023 09:24:08 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
cros-qcom-dts-watchers@...omium.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/4] arm64: dts: qcom: use decimal for cache level
On 16.04.2023 12:11, Krzysztof Kozlowski wrote:
> Cache level is by convention a decimal number, not hex.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Konrad
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 9ff4e9d45065..ece652a0728a 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -83,7 +83,7 @@ CPU3: cpu@3 {
>
> L2_0: l2-cache {
> compatible = "cache";
> - cache-level = <0x2>;
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 84e715aa4310..4056ce59d43f 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -66,7 +66,7 @@ CPU3: cpu@3 {
>
> L2_0: l2-cache {
> compatible = "cache";
> - cache-level = <0x2>;
> + cache-level = <2>;
> };
> };
>
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