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Message-ID: <bf9db17d-56f2-caac-c6ae-376dfc077da7@linaro.org>
Date: Mon, 17 Apr 2023 09:30:54 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5/6] arm64: dts: qcom: sm8550-qrd: add missing PCIE1 PHY
AUX clock frequency
On 16.04.2023 14:37, Krzysztof Kozlowski wrote:
> The SM8550 DTSI defines a fixed PCIE1 PHY AUX clock and expects boards
> to define frequency. Use the same as in MTP8550 to fix:
>
> sm8550-qrd.dtb: pcie-1-phy-aux-clk: 'clock-frequency' is a required property
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Konrad
> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> index d5a645ee2a61..a08aa438bba8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> @@ -359,6 +359,10 @@ vreg_l3g_1p2: ldo3 {
> };
> };
>
> +&pcie_1_phy_aux_clk {
> + clock-frequency = <1000>;
> +};
> +
> &qupv3_id_0 {
> status = "okay";
> };
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