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Message-ID: <20230417073606.25729-7-yong.wu@mediatek.com>
Date: Mon, 17 Apr 2023 15:36:05 +0800
From: Yong Wu <yong.wu@...iatek.com>
To: Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>
CC: Robin Murphy <robin.murphy@....com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Yong Wu <yong.wu@...iatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, <iommu@...ts.linux.dev>,
<linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <mingyuan.ma@...iatek.com>,
<yf.wang@...iatek.com>, <jianjiao.zeng@...iatek.com>,
<chengci.xu@...iatek.com>
Subject: [PATCH v10 6/7] iommu/mediatek: mt8188: Add iova_region_larb_msk
Add iova_region_larb_msk for mt8188. We separate the 16GB iova regions
by each device's larbid/portid.
Refer to include/dt-bindings/memory/mediatek,mt8188-memory-port.h
As commented in the code, larb19(21) means it's larb19 while its SW index
is 21.
Signed-off-by: Yong Wu <yong.wu@...iatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
drivers/iommu/mtk_iommu.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index fa46c4309f35..876624f807d6 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1599,6 +1599,20 @@ static const struct mtk_iommu_plat_data mt8188_data_infra = {
.iova_region_nr = ARRAY_SIZE(single_domain),
};
+static const u32 mt8188_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
+ [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */
+ [1] = {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, ~0, ~0, ~0}, /* Region1: larb19(21)/21(22)/23 */
+ [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */
+ ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
+ ~0, ~0, ~0, ~0, ~0, 0, 0, 0,
+ 0, ~0},
+ [3] = {0},
+ [4] = {[24] = BIT(0) | BIT(1)}, /* Only larb27(24) port0/1 */
+ [5] = {[24] = BIT(2) | BIT(3)}, /* Only larb27(24) port2/3 */
+};
+
static const struct mtk_iommu_plat_data mt8188_data_vdo = {
.m4u_plat = M4U_MT8188,
.flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
@@ -1610,6 +1624,7 @@ static const struct mtk_iommu_plat_data mt8188_data_vdo = {
.banks_enable = {true},
.iova_region = mt8192_multi_dom,
.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .iova_region_larb_msk = mt8188_larb_region_msk,
.larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10,
11 /* 11a */, 25 /* 11c */},
{13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}},
@@ -1626,6 +1641,7 @@ static const struct mtk_iommu_plat_data mt8188_data_vpp = {
.banks_enable = {true},
.iova_region = mt8192_multi_dom,
.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .iova_region_larb_msk = mt8188_larb_region_msk,
.larbid_remap = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID},
{12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID,
16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID,
--
2.25.1
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