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Message-ID: <53d2d5eb-26e-d017-41cc-60292a6f33a6@linux.intel.com>
Date: Mon, 17 Apr 2023 12:19:29 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
cc: Xu Yilun <yilun.xu@...el.com>, Wu Hao <hao.wu@...el.com>,
Tom Rix <trix@...hat.com>, Moritz Fischer <mdf@...nel.org>,
linux-fpga@...r.kernel.org, Lee Jones <lee@...nel.org>,
Jean Delvare <jdelvare@...e.com>,
Guenter Roeck <linux@...ck-us.net>,
Russ Weight <russell.h.weight@...el.com>,
linux-hwmon@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 0/4] intel-m10-bmc: Manage register access to control
delay during sec update
On Mon, 17 Apr 2023, Ilpo Järvinen wrote:
> Manage handshake register access on Max 10 FPGA cards that have a major
> slowdown on reading handshake registers during secure update prepare and
> write phases. The problem does not occur with PMCI-based cards.
>
> The first patch which moves Max M10 symbols into own namespace is
> otherwise independent of the other changes but it would conflict with
> this series if sent as separate change. Thus, it's part of this series
> to give the patches a well-defined order.
>
> Ilpo Järvinen (4):
> mfd: intel-m10-bmc: Move core symbols to own namespace
> mfd: intel-m10-bmc: Create m10bmc_sys_update_bits()
> mfd: intel-m10-bmc: Move m10bmc_sys_read() away from header
> mfd: intel-m10-bmc: Manage access to MAX 10 fw handshake registers
>
> drivers/fpga/intel-m10-bmc-sec-update.c | 47 +++++++------
> drivers/hwmon/intel-m10-bmc-hwmon.c | 1 +
> drivers/mfd/intel-m10-bmc-core.c | 90 ++++++++++++++++++++++++-
> drivers/mfd/intel-m10-bmc-pmci.c | 1 +
> drivers/mfd/intel-m10-bmc-spi.c | 15 +++++
> include/linux/mfd/intel-m10-bmc.h | 43 ++++++++----
> 6 files changed, 163 insertions(+), 34 deletions(-)
>
>
Please disregard v2. I'll send v3 shortly.
(I managed to add the tags into wrong files so they're not correctly
here in v2).
--
i.
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