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Message-ID: <20230417105226.3169-1-quic_kathirav@quicinc.com>
Date:   Mon, 17 Apr 2023 16:22:26 +0530
From:   Kathiravan T <quic_kathirav@...cinc.com>
To:     <andersson@...nel.org>, <agross@...nel.org>,
        <konrad.dybcio@...aro.org>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC:     Kathiravan T <quic_kathirav@...cinc.com>
Subject: [PATCH] clk: qcom: ipq5332: fix the order of SLEEP_CLK and XO clock

The order of DT_SLEEP_CLK and DT_XO are swapped and it is incorrect.
Due to which the clocks for which the parent should be XO is having parent
as SLEEP_CLK and vice versa. So fix the same by re-ordering the entries.

Signed-off-by: Kathiravan T <quic_kathirav@...cinc.com>
---
 drivers/clk/qcom/gcc-ipq5332.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index 8cacbfb10c72..14096887d436 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -20,8 +20,8 @@
 #include "reset.h"
 
 enum {
-	DT_SLEEP_CLK,
 	DT_XO,
+	DT_SLEEP_CLK,
 	DT_PCIE_2LANE_PHY_PIPE_CLK,
 	DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
 	DT_USB_PCIE_WRAPPER_PIPE_CLK,
-- 
2.17.1

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