linux-kernel - linux-next: manual merge of the pci tree with the origin tree

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Message-Id: <20230417124553.765602-1-broonie@kernel.org>
Date:   Mon, 17 Apr 2023 13:45:52 +0100
From:   broonie@...nel.org
To:     Bjorn Helgaas <bhelgaas@...gle.com>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Krzysztof Wilczyński <kw@...ux.com>
Cc:     Basavaraj Natikar <Basavaraj.Natikar@....com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux Next Mailing List <linux-next@...r.kernel.org>,
        Ron Lee <ron.lee@...el.com>, Ron Lee <ron.lee.intel@...il.com>
Subject: linux-next: manual merge of the pci tree with the origin tree

Hi all,

Today's linux-next merge of the pci tree got a conflict in:

  arch/x86/pci/fixup.c

between commit:

  f195fc1e9715b ("x86/PCI: Add quirk for AMD XHCI controller that loses MSI-X state in D3hot")

from the origin tree and commit:

  606012dddebbc ("PCI: Fix up L1SS capability for Intel Apollo Lake Root Port")

from the pci tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc arch/x86/pci/fixup.c
index bf5161dcf89e7,c6c46605812b4..0000000000000
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@@ -826,22 -825,61 +826,81 @@@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_A
  
  #endif
  
 +#ifdef CONFIG_AMD_NB
 +
 +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2                                  0x10136008
 +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK       0x00000080L
 +
 +static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev)
 +{
 +	u32 data;
 +
 +	if (!amd_smn_read(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, &data)) {
 +		data &= ~AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK;
 +		if (amd_smn_write(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, data))
 +			pci_err(dev, "Failed to write data 0x%x\n", data);
 +	} else {
 +		pci_err(dev, "Failed to read data\n");
 +	}
 +}
 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0);
 +#endif
++
+ /*
+  * When returning from D3cold to D0, firmware on some Google Coral and Reef
+  * family Chromebooks with Intel Apollo Lake SoC clobbers the headers of
+  * both the L1 PM Substates capability and the previous capability for the
+  * "Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port B #1".
+  *
+  * Save those values at enumeration-time and restore them at resume.
+  */
+ 
+ static u16 prev_cap, l1ss_cap;
+ static u32 prev_header, l1ss_header;
+ 
+ static void chromeos_save_apl_pci_l1ss_capability(struct pci_dev *dev)
+ {
+ 	int pos = PCI_CFG_SPACE_SIZE, prev = 0;
+ 	u32 header, pheader = 0;
+ 
+ 	while (pos) {
+ 		pci_read_config_dword(dev, pos, &header);
+ 		if (PCI_EXT_CAP_ID(header) == PCI_EXT_CAP_ID_L1SS) {
+ 			prev_cap = prev;
+ 			prev_header = pheader;
+ 			l1ss_cap = pos;
+ 			l1ss_header = header;
+ 			return;
+ 		}
+ 
+ 		prev = pos;
+ 		pheader = header;
+ 		pos = PCI_EXT_CAP_NEXT(header);
+ 	}
+ }
+ 
+ static void chromeos_fixup_apl_pci_l1ss_capability(struct pci_dev *dev)
+ {
+ 	u32 header;
+ 
+ 	if (!prev_cap || !prev_header || !l1ss_cap || !l1ss_header)
+ 		return;
+ 
+ 	/* Fixup the header of L1SS Capability if missing */
+ 	pci_read_config_dword(dev, l1ss_cap, &header);
+ 	if (header != l1ss_header) {
+ 		pci_write_config_dword(dev, l1ss_cap, l1ss_header);
+ 		pci_info(dev, "restore L1SS Capability header (was %#010x now %#010x)\n",
+ 			 header, l1ss_header);
+ 	}
+ 
+ 	/* Fixup the link to L1SS Capability if missing */
+ 	pci_read_config_dword(dev, prev_cap, &header);
+ 	if (header != prev_header) {
+ 		pci_write_config_dword(dev, prev_cap, prev_header);
+ 		pci_info(dev, "restore previous Capability header (was %#010x now %#010x)\n",
+ 			 header, prev_header);
+ 	}
+ }
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability);
+ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability);