linux-kernel - Re: [PATCH v2 3/5] ACPI/PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <dd3e967a-1f1a-9d3e-1058-a5e7951b1dbd@zhaoxin.com>
Date:   Tue, 18 Apr 2023 10:38:58 +0800
From:   LeoLiuoc <LeoLiu-oc@...oxin.com>
To:     Bjorn Helgaas <helgaas@...nel.org>
CC:     <rafael@...nel.org>, <lenb@...nel.org>, <james.morse@....com>,
        <tony.luck@...el.com>, <bp@...en8.de>, <robert.moore@...el.com>,
        <ying.huang@...el.com>, <rdunlap@...radead.org>,
        <bhelgaas@...gle.com>, <linux-acpi@...r.kernel.org>,
        <linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <devel@...ica.org>, <CobeChen@...oxin.com>,
        <TonyWWang@...oxin.com>, <ErosZhang@...oxin.com>,
        <leoliu@...oxin.com>
Subject: Re: [PATCH v2 3/5] ACPI/PCI: Add AER bits #defines for PCIe to
 PCI/PCI-X Bridge



在 2023/4/13 0:10, Bjorn Helgaas 写道:
> On Wed, Apr 12, 2023 at 05:49:55PM +0800, LeoLiuoc wrote:
> 
>>>> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
>>>> index 57b8e2ffb1dd..37f3baa336d7 100644
>>>> --- a/include/uapi/linux/pci_regs.h
>>>> +++ b/include/uapi/linux/pci_regs.h
>>>> @@ -799,6 +799,11 @@
>>>>    #define  PCI_ERR_ROOT_AER_IRQ		0xf8000000 /* Advanced Error Interrupt Message Number */
>>>>    #define PCI_ERR_ROOT_ERR_SRC	0x34	/* Error Source Identification */
>>>> +/* PCIe advanced error reporting extended capabilities for PCIe to PCI/PCI-X Bridge */
>>>> +#define PCI_ERR_UNCOR_MASK2		0x30	/* Secondary Uncorrectable Error Mask */
>>>> +#define PCI_ERR_UNCOR_SEVER2	0x34	/* Secondary Uncorrectable Error Severit */
>>>> +#define PCI_ERR_CAP2			0x38	/* Secondary Advanced Error Capabilities */
>>>
>>> Please squash these right up next to the other PCI_ERR_* definitions
>>> so it's obvious that they overlap PCI_ERR_ROOT_STATUS and
>>> PCI_ERR_ROOT_ERR_SRC (which is fine since one device can't have both),
>>> e.g.,
>>>
>>>     #define PCI_ERR_ROOT_STATUS     0x30
>>>     #define  PCI_ERR_ROOT_COR_RCV           0x00000001 /* ERR_COR Received */
>>>     ...
>>>     #define PCI_ERR_ROOT_ERR_SRC    0x34    /* Error Source Identification */
>>>     #define PCI_ERR_UNCOR_MASK2     0x30    /* PCIe to PCI/PCI-X bridge */
>>>     #define PCI_ERR_UNCOR_SEVER2    0x34    /* PCIe to PCI/PCI-X bridge */
>>>     #define PCI_ERR_CAP2            0x38    /* PCIe to PCI/PCI-X bridge */
>>
>> I don't seem to understand what you mean. PCI_ERR_UNCOR_MASK2,
>> PCI_ERR_UNCOR_SEVER2, and PCI_ERR_CAP2 represent the control and handling of
>> individual errors that occur on traditional PCI or PCI-x secondary bus
>> interfaces, these registers are valid only for Bridge. Although
>> PCI_ERR_ROOT_ERR_SRC and PCI_ERR_UNCOR_SEVER2 have the same value, they
>> represent register definitions for different device types.
> 
> Right.  I just don't want the blank line in the middle because it
> might be mistaken for items in a different capability.  All the other
> AER capability registers are defined together in a block, with no
> blank lines in the middle, so I think these new ones should be part of
> that block.
> 
> Bjorn

Ok，I see your point. Do you think this line of comment is still necessary?
/* PCIe advanced error reporting extended capabilities for PCIe to 
PCI/PCI-X Bridge */

Yours sincerely,
Leoliu-oc