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Message-ID: <fa84facd-9b13-388f-5f22-a287f7aa403f@linaro.org>
Date: Wed, 19 Apr 2023 12:54:22 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Devi Priya <quic_devipriy@...cinc.com>, agross@...nel.org,
andersson@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, mturquette@...libre.com,
sboyd@...nel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org
Cc: quic_srichara@...cinc.com, quic_sjaganat@...cinc.com,
quic_kathirav@...cinc.com, quic_arajkuma@...cinc.com,
quic_anusha@...cinc.com, quic_poovendh@...cinc.com
Subject: Re: [PATCH V2 3/4] arm64: dts: qcom: ipq9574: Drop
bias_pll_ubi_nc_clk & update intc node
On 17.04.2023 07:33, Devi Priya wrote:
> Drop the unused backup source bias_pll_ubi_nc_clk.
> Also, update the size of GICC and GICV region to 8kB and add target CPU
> encoding.
These things have too big and too distant consequences to go in
a single patch and the GIC fix should have a fixes tag.
>
> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 13 +++----------
> 1 file changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 3bb7435f5e7f..f1f959b43180 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -16,12 +16,6 @@
> #size-cells = <2>;
>
> clocks {
> - bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk {
> - compatible = "fixed-clock";
> - clock-frequency = <353000000>;
> - #clock-cells = <0>;
> - };
> -
> sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -131,7 +125,6 @@
> reg = <0x01800000 0x80000>;
> clocks = <&xo_board_clk>,
> <&sleep_clk>,
> - <&bias_pll_ubi_nc_clk>,
NAK, this is an ABI break. If you want to drop it, you'd need
to leave a <0> here.
Konrad
> <0>,
> <0>,
> <0>,
> @@ -172,14 +165,14 @@
> intc: interrupt-controller@...0000 {
> compatible = "qcom,msm-qgic2";
> reg = <0x0b000000 0x1000>, /* GICD */
> - <0x0b002000 0x1000>, /* GICC */
> + <0x0b002000 0x2000>, /* GICC */
> <0x0b001000 0x1000>, /* GICH */
> - <0x0b004000 0x1000>; /* GICV */
> + <0x0b004000 0x2000>; /* GICV */
> #address-cells = <1>;
> #size-cells = <1>;
> interrupt-controller;
> #interrupt-cells = <3>;
> - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> ranges = <0 0x0b00c000 0x3000>;
>
> v2m0: v2m@0 {
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