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Message-Id: <20230419111111.477118-7-dfustini@baylibre.com>
Date: Wed, 19 Apr 2023 04:10:56 -0700
From: Drew Fustini <dfustini@...libre.com>
To: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Ved Shanbhogue <ved@...osinc.com>,
Kornel Dulęba <mindal@...ihalf.com>,
Adrien Ricciardi <aricciardi@...libre.com>,
Nicolas Pitre <npitre@...libre.com>,
Fenghua Yu <fenghua.yu@...el.com>,
Reinette Chatre <reinette.chatre@...el.com>,
Babu Moger <babu.moger@....com>,
Peter Newman <peternewman@...gle.com>, x86@...nel.org,
Rob Herring <robh+dt@...nel.org>,
James Morse <james.morse@....com>
Cc: Drew Fustini <dfustini@...libre.com>
Subject: [RFC PATCH 06/21] RISC-V: QoS: define CBQRI resctrl resources and domains
Define data structures to encapsulate the resctrl resource
and domain structures.
Co-developed-by: Adrien Ricciardi <aricciardi@...libre.com>
Signed-off-by: Adrien Ricciardi <aricciardi@...libre.com>
Signed-off-by: Drew Fustini <dfustini@...libre.com>
---
arch/riscv/kernel/qos/internal.h | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/riscv/kernel/qos/internal.h b/arch/riscv/kernel/qos/internal.h
index e07d7f92e206..a3ed98ce5dd6 100644
--- a/arch/riscv/kernel/qos/internal.h
+++ b/arch/riscv/kernel/qos/internal.h
@@ -65,6 +65,11 @@
#define CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT 2
#define CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS 1
+int qos_resctrl_setup(void);
+void qos_resctrl_exit(void);
+int qos_resctrl_online_cpu(unsigned int cpu);
+int qos_resctrl_offline_cpu(unsigned int cpu);
+
/* Capacity Controller hardware capabilities */
/* from qemu/include/hw/riscv/cbqri.h */
struct riscv_cbqri_capacity_caps {
@@ -127,4 +132,26 @@ struct cbqri_controller {
bool mon_capable;
};
+struct cbqri_resctrl_res {
+ struct rdt_resource resctrl_res;
+ struct cbqri_controller controller;
+ u32 max_rcid;
+ u32 max_mcid;
+};
+
+struct cbqri_resctrl_dom {
+ struct rdt_domain resctrl_dom;
+ // NCBLKS is 16 bit which is 2^16 = 65536
+ // If each bit is a block, then cc_block_mask could 1024 times 64 byte
+ u64 cbm;
+ u64 rbwb;
+ u64 *ctrl_val;
+ struct cbqri_controller *hw_ctrl;
+};
+
+struct cbqri_config {
+ u64 cbm; /* capacity block mask */
+ u64 rbwb; /* reserved bandwidth blocks */
+};
+
#endif /* _ASM_RISCV_QOS_INTERNAL_H */
--
2.34.1
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