linux-kernel - [RFC PATCH 12/21] dt-bindings: riscv: add riscv,cbqri bindings

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Message-Id: <20230419111111.477118-13-dfustini@baylibre.com>
Date:   Wed, 19 Apr 2023 04:11:02 -0700
From:   Drew Fustini <dfustini@...libre.com>
To:     linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Ved Shanbhogue <ved@...osinc.com>,
        Kornel Dulęba <mindal@...ihalf.com>,
        Adrien Ricciardi <aricciardi@...libre.com>,
        Nicolas Pitre <npitre@...libre.com>,
        Fenghua Yu <fenghua.yu@...el.com>,
        Reinette Chatre <reinette.chatre@...el.com>,
        Babu Moger <babu.moger@....com>,
        Peter Newman <peternewman@...gle.com>, x86@...nel.org,
        Rob Herring <robh+dt@...nel.org>,
        James Morse <james.morse@....com>
Cc:     Drew Fustini <dfustini@...libre.com>
Subject: [RFC PATCH 12/21] dt-bindings: riscv: add riscv,cbqri bindings

Document properties that can be used in the bindings for controllers
that implement the RISC-V CBQRI specification.

Co-developed-by: Adrien Ricciardi <aricciardi@...libre.com>
Signed-off-by: Adrien Ricciardi <aricciardi@...libre.com>
Signed-off-by: Drew Fustini <dfustini@...libre.com>
---
 .../bindings/riscv/riscv,cbqri.yaml           | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml

diff --git a/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml b/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml
new file mode 100644
index 000000000000..3f017c6b1fb1
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/riscv,cbqri.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Capacity and Bandwidth Register Interface (CBQRI) properties
+
+description: |
+  Common properties for cache and memory controllers that implement the
+  RISC-V CBQRI specification:
+  https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf
+
+maintainers:
+  - Drew Fustini <dfustini@...libre.com>
+
+properties:
+  riscv,cbqri-rcid:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: The maximum number of RCIDs the controller supports
+
+  riscv,cbqri-mcid:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: The maximum number of MCIDs the controller supports
+
+additionalProperties: true
+
+...
-- 
2.34.1